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[AArch64] support neon_sshl and neon_ushl in performIntrinsicCombine.
Try to generate ushll/sshll for aarch64_neon_ushl/aarch64_neon_sshl, if their first operand is extended and the second operand is a constant Also adds a few tests marked with FIXME, where we can further increase codegen. Reviewers: t.p.northover, samparker, dmgreen, anemet Reviewed By: anemet Differential Revision: https://reviews.llvm.org/D62308 llvm-svn: 372565
This commit is contained in:
Florian Hahn
parent
d93fa5ac8a
commit
b156528748
@ -10332,6 +10332,29 @@ static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
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Opcode = AArch64ISD::SQSHLU_I;
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IsRightShift = false;
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break;
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case Intrinsic::aarch64_neon_sshl:
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case Intrinsic::aarch64_neon_ushl: {
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// ushll/ushll2 provide unsigned shifts with immediate operands and
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// sshll/sshll2 provide signed shifts with immediates, so we have to make
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// sure we only match patterns here we can later match to them.
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SDValue Op0 = N->getOperand(1);
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if (Op0.getNode()->getOpcode() != (IID == Intrinsic::aarch64_neon_ushl
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? ISD::ZERO_EXTEND
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: ISD::SIGN_EXTEND))
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return SDValue();
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EVT FromType = Op0.getOperand(0).getValueType();
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EVT ToType = Op0.getValueType();
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unsigned FromSize = FromType.getScalarSizeInBits();
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if (!FromType.isVector() || !ToType.isVector() ||
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(FromSize != 8 && FromSize != 16 && FromSize != 32) ||
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2 * FromSize != ToType.getScalarSizeInBits())
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return SDValue();
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Opcode = AArch64ISD::VSHL;
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IsRightShift = false;
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break;
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}
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}
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if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
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@ -10418,6 +10441,8 @@ static SDValue performIntrinsicCombine(SDNode *N,
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case Intrinsic::aarch64_neon_sqshlu:
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case Intrinsic::aarch64_neon_srshl:
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case Intrinsic::aarch64_neon_urshl:
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case Intrinsic::aarch64_neon_sshl:
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case Intrinsic::aarch64_neon_ushl:
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return tryCombineShiftImm(IID, N, DAG);
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case Intrinsic::aarch64_crc32b:
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case Intrinsic::aarch64_crc32cb:
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@ -1192,6 +1192,100 @@ define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind {
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ret <2 x i64> %tmp3
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}
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declare <16 x i8> @llvm.aarch64.neon.ushl.v16i8(<16 x i8>, <16 x i8>)
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declare <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16>, <8 x i16>)
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declare <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32>, <4 x i32>)
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declare <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64>, <2 x i64>)
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define <8 x i16> @neon.ushll8h_constant_shift(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: neon.ushll8h_constant_shift
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;CHECK: ushll.8h v0, {{v[0-9]+}}, #1
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
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ret <8 x i16> %tmp3
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}
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define <8 x i16> @neon.ushl8h_no_constant_shift(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: neon.ushl8h_no_constant_shift
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;CHECK: ushl.8h v0, v0, v0
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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; Here we do not extend to the double the bitwidth, so we cannot fold to ushll.
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define <4 x i32> @neon.ushll8h_constant_shift_extend_not_2x(<4 x i8>* %A) nounwind {
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;CHECK-LABEL: @neon.ushll8h_constant_shift_extend_not_2x
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;CHECK-NOT: ushll.8h v0,
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;CHECK: ldrb w8, [x0]
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;CHECK: movi.4s v1, #1
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;CHECK: fmov s0, w8
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;CHECK: ldrb w8, [x0, #1]
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;CHECK: mov.s v0[1], w8
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;CHECK: ldrb w8, [x0, #2]
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;CHECK: mov.s v0[2], w8
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;CHECK: ldrb w8, [x0, #3]
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;CHECK: mov.s v0[3], w8
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;CHECK: ushl.4s v0, v0, v1
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%tmp1 = load <4 x i8>, <4 x i8>* %A
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%tmp2 = zext <4 x i8> %tmp1 to <4 x i32>
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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define <8 x i16> @neon.ushl8_noext_constant_shift(<8 x i16>* %A) nounwind {
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; CHECK-LABEL: neon.ushl8_noext_constant_shift
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; CHECK: ldr q0, [x0]
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; CHECK-NEXT: movi.8h v1, #1
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; CHECK-NEXT: ushl.8h v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @neon.ushll4s_constant_shift(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: neon.ushll4s_constant_shift
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;CHECK: ushll.4s v0, {{v[0-9]+}}, #1
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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; FIXME: unnecessary ushll.4s v0, v0, #0?
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define <4 x i32> @neon.ushll4s_neg_constant_shift(<4 x i16>* %A) nounwind {
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; CHECK-LABEL: neon.ushll4s_neg_constant_shift
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; CHECK: movi.2d v1, #0xffffffffffffffff
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; CHECK: ushll.4s v0, v0, #0
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; CHECK: ushl.4s v0, v0, v1
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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ret <4 x i32> %tmp3
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}
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; FIXME: should be constant folded.
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define <4 x i32> @neon.ushll4s_constant_fold() nounwind {
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; CHECK-LABEL: neon.ushll4s_constant_fold
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; CHECK: movi.4s v1, #1
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; CHECK-NEXT: ushl.4s v0, v0, v1
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;
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @neon.ushll2d_constant_shift(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: neon.ushll2d_constant_shift
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;CHECK: ushll.2d v0, {{v[0-9]+}}, #1
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)
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ret <2 x i64> %tmp3
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}
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define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: sshll8h:
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;CHECK: sshll.8h v0, {{v[0-9]+}}, #1
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@ -1201,15 +1295,6 @@ define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind {
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: sshll4s:
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;CHECK: sshll.4s v0, {{v[0-9]+}}, #1
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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%tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: sshll2d:
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;CHECK: sshll.2d v0, {{v[0-9]+}}, #1
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@ -1219,6 +1304,99 @@ define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind {
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ret <2 x i64> %tmp3
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}
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declare <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8>, <16 x i8>)
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declare <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16>, <8 x i16>)
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declare <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32>, <4 x i32>)
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declare <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64>, <2 x i64>)
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define <16 x i8> @neon.sshl16b_constant_shift(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: neon.sshl16b_constant_shift
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;CHECK: sshl.16b {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @neon.sshll8h_constant_shift(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: neon.sshll8h_constant_shift
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;CHECK: sshll.8h v0, {{v[0-9]+}}, #1
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @neon.sshl4s_wrong_ext_constant_shift(<4 x i8>* %A) nounwind {
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;CHECK-LABEL: neon.sshl4s_wrong_ext_constant_shift
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;CHECK: sshl.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%tmp1 = load <4 x i8>, <4 x i8>* %A
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%tmp2 = sext <4 x i8> %tmp1 to <4 x i32>
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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define <4 x i32> @neon.sshll4s_constant_shift(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: neon.sshll4s_constant_shift
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;CHECK: sshll.4s v0, {{v[0-9]+}}, #1
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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define <4 x i32> @neon.sshll4s_neg_constant_shift(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: neon.sshll4s_neg_constant_shift
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;CHECK: movi.2d v1, #0xffffffffffffffff
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;CHECK: sshll.4s v0, v0, #0
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;CHECK: sshl.4s v0, v0, v1
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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ret <4 x i32> %tmp3
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}
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; FIXME: should be constant folded.
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define <4 x i32> @neon.sshl4s_constant_fold() nounwind {
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;CHECK-LABEL: neon.sshl4s_constant_fold
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;CHECK: sshl.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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define <4 x i32> @neon.sshl4s_no_fold(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: neon.sshl4s_no_fold
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;CHECK: sshl.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @neon.sshll2d_constant_shift(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: neon.sshll2d_constant_shift
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;CHECK: sshll.2d v0, {{v[0-9]+}}, #1
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)
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ret <2 x i64> %tmp3
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}
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; FIXME: should be constant folded.
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define <2 x i64> @neon.sshl2d_constant_fold() nounwind {
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;CHECK-LABEL: neon.sshl2d_constant_fold
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;CHECK: sshl.2d {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> <i64 99, i64 1000>, <2 x i64> <i64 1, i64 1>)
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ret <2 x i64> %tmp3
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}
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define <2 x i64> @neon.sshl2d_no_fold(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: neon.sshl2d_no_fold
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;CHECK: sshl.2d {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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%tmp2 = load <2 x i64>, <2 x i64>* %A
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 2, i64 2>)
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ret <2 x i64> %tmp3
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}
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define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: sshll2_8h:
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;CHECK: sshll.8h v0, {{v[0-9]+}}, #1
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