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switch TargetLowering::getConstraintType to take the entire constraint,

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not just the first letter.  No functionality change.

llvm-svn: 35322
This commit is contained in:
Chris Lattner 2007-03-25 02:14:49 +00:00
parent 676eeb9c94
commit b19069959d
11 changed files with 82 additions and 68 deletions
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6
include/llvm/Target/TargetLowering.h
View File

@ -806,9 +806,9 @@ public:
C_Unknown // Unsupported constraint.
};
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
virtual ConstraintType getConstraintType(char ConstraintLetter) const;
/// getConstraintType - Given a constraint, return the type of constraint it
/// is for this target.
virtual ConstraintType getConstraintType(const std::string &Constraint) const;
/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),

8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -2633,9 +2633,9 @@ static std::string GetMostGeneralConstraint(std::vector<std::string> &C,
std::string *Current = &C[0];
// If we have multiple constraints, try to pick the most general one ahead
// of time. This isn't a wonderful solution, but handles common cases.
TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0][0]);
TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
for (unsigned j = 1, e = C.size(); j != e; ++j) {
TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j][0]);
TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
if (getConstraintGenerality(ThisFlavor) >
getConstraintGenerality(Flavor)) {
// This constraint letter is more general than the previous one,
@ -2748,7 +2748,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
case InlineAsm::isOutput: {
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (ConstraintCode.size() == 1) // not a physreg name.
CTy = TLI.getConstraintType(ConstraintCode[0]);
CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Memory) {
// Memory output.
@ -2863,7 +2863,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (ConstraintCode.size() == 1) // not a physreg name.
CTy = TLI.getConstraintType(ConstraintCode[0]);
CTy = TLI.getConstraintType(ConstraintCode);
if (CTy == TargetLowering::C_Other) {
InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,

44
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1828,28 +1828,32 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
//===----------------------------------------------------------------------===//
TargetLowering::ConstraintType
TargetLowering::getConstraintType(char ConstraintLetter) const {
TargetLowering::getConstraintType(const std::string &Constraint) const {
// FIXME: lots more standard ones to handle.
switch (ConstraintLetter) {
default: return C_Unknown;
case 'r': return C_RegisterClass;
case 'm': // memory
case 'o': // offsetable
case 'V': // not offsetable
return C_Memory;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': // Relocatable Constant
case 'I': // Target registers.
case 'J':
case 'K':
case 'L':
case 'M':
case 'N':
case 'O':
case 'P':
return C_Other;
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
case 'r': return C_RegisterClass;
case 'm': // memory
case 'o': // offsetable
case 'V': // not offsetable
return C_Memory;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': // Relocatable Constant
case 'I': // Target registers.
case 'J':
case 'K':
case 'L':
case 'M':
case 'N':
case 'O':
case 'P':
return C_Other;
}
}
// TODO: Handle registers.
return C_Unknown;
}
/// isOperandValidForConstraint - Return the specified operand (possibly

12
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1550,12 +1550,14 @@ void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
ARMTargetLowering::ConstraintType
ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
switch (ConstraintLetter) {
case 'l':
return C_RegisterClass;
default: return TargetLowering::getConstraintType(ConstraintLetter);
ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
case 'l': return C_RegisterClass;
}
}
return TargetLowering::getConstraintType(Constraint);
}
std::pair<unsigned, const TargetRegisterClass*>

2
lib/Target/ARM/ARMISelLowering.h
View File

@ -133,7 +133,7 @@ namespace llvm {
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const;
ConstraintType getConstraintType(char ConstraintLetter) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;

18
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -571,14 +571,16 @@ SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
AlphaTargetLowering::ConstraintType
AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
switch (ConstraintLetter) {
default: break;
case 'f':
case 'r':
return C_RegisterClass;
}
return TargetLowering::getConstraintType(ConstraintLetter);
AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
case 'f':
case 'r':
return C_RegisterClass;
}
}
return TargetLowering::getConstraintType(Constraint);
}
std::vector<unsigned> AlphaTargetLowering::

2
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -81,7 +81,7 @@ namespace llvm {
bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG);
ConstraintType getConstraintType(char ConstraintLetter) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,

26
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -3105,20 +3105,22 @@ void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
}
/// getConstraintType - Given a constraint letter, return the type of
/// getConstraintType - Given a constraint, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
switch (ConstraintLetter) {
default: break;
case 'b':
case 'r':
case 'f':
case 'v':
case 'y':
return C_RegisterClass;
}
return TargetLowering::getConstraintType(ConstraintLetter);
PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
case 'b':
case 'r':
case 'f':
case 'v':
case 'y':
return C_RegisterClass;
}
}
return TargetLowering::getConstraintType(Constraint);
}
std::pair<unsigned, const TargetRegisterClass*>

2
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -229,7 +229,7 @@ namespace llvm {
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
ConstraintType getConstraintType(char ConstraintLetter) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;

28
lib/Target/X86/X86ISelLowering.cpp
View File

@ -4521,19 +4521,23 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
X86TargetLowering::ConstraintType
X86TargetLowering::getConstraintType(char ConstraintLetter) const {
switch (ConstraintLetter) {
case 'A':
case 'r':
case 'R':
case 'l':
case 'q':
case 'Q':
case 'x':
case 'Y':
return C_RegisterClass;
default: return TargetLowering::getConstraintType(ConstraintLetter);
X86TargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'A':
case 'r':
case 'R':
case 'l':
case 'q':
case 'Q':
case 'x':
case 'Y':
return C_RegisterClass;
default:
break;
}
}
return TargetLowering::getConstraintType(Constraint);
}
/// isOperandValidForConstraint - Return the specified operand (possibly

2
lib/Target/X86/X86ISelLowering.h
View File

@ -316,7 +316,7 @@ namespace llvm {
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
ConstraintType getConstraintType(char ConstraintLetter) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,