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Revert "[Support] make report_fatal_error abort instead of exit"

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This reverts commit 647c3f4e47de8a850ffcaa897db68702d8d2459a.

Got bots failure from sanitizer-windows and maybe others.
This commit is contained in:
Yuanfang Chen 2020-01-15 17:46:18 -08:00
parent 725cd0da61
commit b1c09bbef0
319 changed files with 450 additions and 433 deletions
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4
docs/ProgrammersManual.rst
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@ -453,8 +453,8 @@ recovery.
LLVM, there are places where this hasn't been practical to apply. In
situations where you absolutely must emit a non-programmatic error and
the ``Error`` model isn't workable you can call ``report_fatal_error``,
which will call installed error handlers, print a message, and abort the
program. The use of `report_fatal_error` in this case is discouraged.
which will call installed error handlers, print a message, and exit the
program.
Recoverable errors are modeled using LLVM's ``Error`` scheme. This scheme
represents errors using function return values, similar to classic C integer

2
include/llvm/Support/ErrorHandling.h
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@ -66,7 +66,7 @@ class StringRef;
///
/// If no error handler is installed the default is to print the message to
/// standard error, followed by a newline.
/// After the error handler is called this function will call abort(), it
/// After the error handler is called this function will call exit(1), it
/// does not return.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason,
bool gen_crash_diag = true);

2
lib/Support/ErrorHandling.cpp
View File

@ -122,7 +122,7 @@ void llvm::report_fatal_error(const Twine &Reason, bool GenCrashDiag) {
// files registered with RemoveFileOnSignal.
sys::RunInterruptHandlers();
abort();
exit(1);
}
void llvm::install_bad_alloc_error_handler(fatal_error_handler_t handler,

2
test/Assembler/datalayout-invalid-function-ptr-alignment.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llvm-as %s 2>&1 | FileCheck %s
; RUN: not llvm-as %s 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2

2
test/Assembler/datalayout-invalid-stack-natural-alignment.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llvm-as %s 2>&1 | FileCheck %s
; RUN: not llvm-as %s 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2

2
test/Assembler/getInt.ll
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@ -1,3 +1,3 @@
; RUN: not --crash opt < %s 2>&1 | grep 'not a number, or does not fit in an unsigned int'
; RUN: not opt < %s 2>&1 | grep 'not a number, or does not fit in an unsigned int'
target datalayout = "p:4294967296:64:64"

2
test/Assembler/invalid-datalayout-alloca-addrspace.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "A16777216"
; CHECK: Invalid address space, must be a 24-bit integer

2
test/Assembler/invalid-datalayout-program-addrspace.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
; CHECK: Invalid address space, must be a 24-bit integer
target datalayout = "P16777216"

2
test/Assembler/invalid-datalayout1.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "^"
; CHECK: Unknown specifier in datalayout string

2
test/Assembler/invalid-datalayout10.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "m"
; CHECK: Expected mangling specifier in datalayout string

2
test/Assembler/invalid-datalayout11.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "m."
; CHECK: Unexpected trailing characters after mangling specifier in datalayout string

2
test/Assembler/invalid-datalayout12.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "f"
; CHECK: Missing alignment specification in datalayout string

2
test/Assembler/invalid-datalayout13.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = ":32"
; CHECK: Expected token before separator in datalayout string

2
test/Assembler/invalid-datalayout14.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "i64:64:16"
; CHECK: Preferred alignment cannot be less than the ABI alignment

2
test/Assembler/invalid-datalayout15.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "i64:16:16777216"
; CHECK: Invalid preferred alignment, must be a 16bit integer

2
test/Assembler/invalid-datalayout16.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "i64:16777216:16777216"
; CHECK: Invalid ABI alignment, must be a 16bit integer

2
test/Assembler/invalid-datalayout17.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "i16777216:16:16"
; CHECK: Invalid bit width, must be a 24bit integer

2
test/Assembler/invalid-datalayout18.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "p:32:32:16"
; CHECK: Preferred alignment cannot be less than the ABI alignment

2
test/Assembler/invalid-datalayout19.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "p:0:32:32"

2
test/Assembler/invalid-datalayout2.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "m:v"
; CHECK: Unknown mangling in datalayout string

2
test/Assembler/invalid-datalayout20.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "p:64:24:64"

2
test/Assembler/invalid-datalayout21.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "p:64:64:24"

2
test/Assembler/invalid-datalayout22.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "v128:0:128"

2
test/Assembler/invalid-datalayout23.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "i32:24:32"

2
test/Assembler/invalid-datalayout24.ll
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@ -1,4 +1,4 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "i32:32:24"

2
test/Assembler/invalid-datalayout3.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "n0"
; CHECK: Zero width native integer type in datalayout string

2
test/Assembler/invalid-datalayout4.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "p16777216:64:64:64"
; CHECK: Invalid address space, must be a 24bit integer

2
test/Assembler/invalid-datalayout5.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "a1:64"
; CHECK: Sized aggregate specification in datalayout string

2
test/Assembler/invalid-datalayout6.ll
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@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "a:"
; CHECK: Trailing separator in datalayout string

2
test/Assembler/invalid-datalayout7.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "p:52"
; CHECK: number of bits must be a byte width multiple

2
test/Assembler/invalid-datalayout8.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "e-p"
; CHECK: Missing size specification for pointer in datalayout string

2
test/Assembler/invalid-datalayout9.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
target datalayout = "e-p:64"
; CHECK: Missing alignment specification for pointer in datalayout string

2
test/Bitcode/function-default-address-spaces.ll
View File

@ -1,6 +1,6 @@
; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s -check-prefixes CHECK,PROG-AS0
; RUN: llvm-as -data-layout "P200" %s -o - | llvm-dis | FileCheck %s -check-prefixes CHECK,PROG-AS200
; RUN: not --crash llvm-as -data-layout "P123456789" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix BAD-DATALAYOUT
; RUN: not llvm-as -data-layout "P123456789" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix BAD-DATALAYOUT
; BAD-DATALAYOUT: LLVM ERROR: Invalid address space, must be a 24-bit integer
; PROG-AS0-NOT: target datalayout

2
test/Bitcode/invalid-functionptr-align.ll
View File

@ -1,5 +1,5 @@
; Bitcode with invalid function pointer alignment.
; RUN: not --crash llvm-dis %s.bc -o - 2>&1 | FileCheck %s
; RUN: not llvm-dis %s.bc -o - 2>&1 | FileCheck %s
CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2

12
test/Bitcode/invalid.test
View File

@ -1,6 +1,6 @@
RUN: not llvm-dis -disable-output %p/Inputs/invalid-empty.bc 2>&1 | \
RUN: FileCheck --check-prefix=INVALID-EMPTY %s
RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \
RUN: not llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \
RUN: FileCheck --check-prefix=INVALID-ENCODING %s
RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev.bc 2>&1 | \
RUN: FileCheck --check-prefix=BAD-ABBREV %s
@ -71,14 +71,14 @@ RUN: FileCheck --check-prefix=FP-SHIFT %s
FP-SHIFT: Invalid record
RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \
RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \
RUN: FileCheck --check-prefix=HUGE-ABBREV-OP %s
RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \
RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \
RUN: FileCheck --check-prefix=HUGE-ABBREV-OP %s
HUGE-ABBREV-OP: Fixed or VBR abbrev record with size > MaxChunkData
RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \
RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \
RUN: FileCheck --check-prefix=ARRAY-TYPE %s
ARRAY-TYPE: Array element type can't be an Array or a Blob
@ -116,7 +116,7 @@ RUN: FileCheck --check-prefix=INVALID-CAST %s
INVALID-CAST: Invalid cast
RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \
RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \
RUN: FileCheck --check-prefix=ARRAY-NOT-2LAST %s
ARRAY-NOT-2LAST: Array op not second to last
@ -176,7 +176,7 @@ RUN: FileCheck --check-prefix=INVALID-GVCOMDAT-ID %s
INVALID-GVCOMDAT-ID: Invalid global variable comdat ID
RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \
RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \
RUN: FileCheck --check-prefix=ABBREV-NO-OPS %s
ABBREV-NO-OPS: Abbrev record with no operands

4
test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
View File

@ -1,9 +1,9 @@
; RUN: not --crash llc -O0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
; RUN: not llc -O0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
; RUN: llc -O0 -global-isel -global-isel-abort=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=FALLBACK
; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
; RUN: not --crash llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN
; RUN: not llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN
; This file checks that the fallback path to selection dag works.
; The test is fragile in the sense that it must be updated to expose
; something that fails with global-isel.

2
test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc %s -mtriple aarch64-apple-darwin -debug-only=aarch64-call-lowering -global-isel -global-isel-abort=2 -o - 2>&1 | FileCheck %s
; RUN: not llc %s -mtriple aarch64-apple-darwin -debug-only=aarch64-call-lowering -global-isel -global-isel-abort=2 -o - 2>&1 | FileCheck %s
; REQUIRES: asserts
; Verify that we fall back to SelectionDAG, and error out when we can't tail call musttail functions

3
test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir
View File

@ -1,4 +1,5 @@
# RUN: not --crash llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s
# RUN: not llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s
# REQUIRES: asserts
# This is to demonstrate what kind of bugs we're missing w/o some kind
# of validation for LegalizerInfo: G_INTTOPTR could only be legal /

3
test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir
View File

@ -1,4 +1,5 @@
# RUN: not --crash llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s
# RUN: not llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s
# REQUIRES: asserts
# This is to demonstrate what kind of bugs we're missing w/o some kind
# of validation for LegalizerInfo: G_INTTOPTR could only be legal /

2
test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s
; RUN: not llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"

4
test/CodeGen/AArch64/arm64-named-reg-alloc.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
define i32 @get_stack() nounwind {
entry:

4
test/CodeGen/AArch64/arm64-named-reg-notareg.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
define i32 @get_stack() nounwind {
entry:

2
test/CodeGen/AArch64/arm64-tls-dynamics.ll
View File

@ -5,7 +5,7 @@
; FIXME: We currently produce "small" code for the tiny model
; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=tiny -verify-machineinstrs < %s | FileCheck %s
; FIXME: We currently error for the large code model
; RUN: not --crash llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE
; RUN: not llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE
; CHECK-LARGE: ELF TLS only supported in small memory model

2
test/CodeGen/AArch64/arm64-tls-initial-exec.ll
View File

@ -3,7 +3,7 @@
; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=tiny < %s | FileCheck %s --check-prefix=CHECK-TINY
; RUN: llc -mtriple=arm64-none-linux-gnu -filetype=obj < %s -code-model=tiny | llvm-objdump -r - | FileCheck --check-prefix=CHECK-TINY-RELOC %s
; FIXME: We currently error for the large code model
; RUN: not --crash llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE
; RUN: not llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE
; CHECK-LARGE: ELF TLS only supported in small memory model

2
test/CodeGen/AArch64/fast-isel-sp-adjust.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -O0 -fast-isel -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
; RUN: not --crash llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t
; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t
; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t
; The issue here is that FastISel cannot emit an ADDrr where one of the inputs

2
test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s
; RUN: not llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s
; Numbers smaller than -127 and greater than or equal to 127 are not allowed.
; This should get lowered to a regular vector multiply and these tests should

2
test/CodeGen/AArch64/sve-neg-int-arith-imm.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s
; RUN: not llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s
; Numbers smaller than -127 and greater than or equal to 127 allowed for imm mul.
; This should get lowered to a regular vector multiply and these tests should

6
test/CodeGen/AArch64/tiny_supported.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s
; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; RUN: not llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY
; CHECK-NOT: tiny code model is only supported on ELF
; CHECK-LABEL: foo

2
test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -global-isel -march=amdgcn -mcpu=tonga < %S/../lds-zero-initializer.ll 2>&1 | FileCheck %s
; RUN: not llc -global-isel -march=amdgcn -mcpu=tonga < %S/../lds-zero-initializer.ll 2>&1 | FileCheck %s
; FIXME: Select should succeed
; CHECK: error: <unknown>:0:0: in function load_zeroinit_lds_global void (i32 addrspace(1)*, i1): unsupported initializer for address space

2
test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s
# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s
# This needs to be expanded into a cmpxchg loop.
# TODO: Will AtomicExpand still do this?

2
test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
View File

@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -o - %s | FileCheck %s
# RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_XCHG %0:_(p0), %1:_ :: (load store seq_cst 4) (in function: atomicrmw_xchg_flat_i32)

2
test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s
# RUN: not llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: LLVM ERROR: unable to legalize instruction: %3:_(p0) = G_JUMP_TABLE %jump-table.0 (in function: jt_test)

2
test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 | FileCheck %s
# RUN: not llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 | FileCheck %s
# CHECK: LLVM ERROR: unable to legalize instruction: %1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0:_(<2 x s1>) (in function: test_unmerge_v2s1)

4
test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
View File

@ -1,5 +1,5 @@
# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s
# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s
# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s
# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s
# Check behavior for illegal copies.

2
test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s
# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: *** Bad machine code: No live subrange at use ***
# CHECK-NEXT: - function: at_least_one_value_should_be_defined_by_this_mask

2
test/CodeGen/AMDGPU/branch-relax-spill.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s
; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s
; FIXME: This should be able to compile, but requires inserting an
; extra block to restore the scavenged register.

2
test/CodeGen/AMDGPU/call-to-kernel-undefined.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; FIXME: It should be invalid IR to have a call to a kernel, but this
; is currently relied on, but should be eliminated before codegen.

2
test/CodeGen/AMDGPU/call-to-kernel.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; FIXME: It should be invalid IR to have a call to a kernel, but this
; is currently relied on, but should be eliminated before codegen.

6
test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
View File

@ -1,6 +1,6 @@
; RUN: not --crash llc -march=amdgcn -mcpu=verde -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=verde -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
;CHECK: LLVM ERROR: unable to allocate function argument
define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } @_amdgpu_gs_sgpr_i32 (i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg) {

2
test/CodeGen/AMDGPU/div_i128.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: unsupported libcall legalization
define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {

6
test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
View File

@ -1,8 +1,8 @@
; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck -check-prefix=HSA-DEFAULT %s
; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; Flat instructions should not select if the target device doesn't
; support them. The default device should be able to select for HSA.

4
test/CodeGen/AMDGPU/lds-initializer.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
; CHECK: lds: unsupported initializer for address space

4
test/CodeGen/AMDGPU/lds-zero-initializer.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
; CHECK: lds: unsupported initializer for address space

2
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR %s
; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s

2
test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: invalid register "flat_scratch_lo" for subtarget.

2
test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: invalid type for register "exec".

2
test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s
; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: invalid type for register "m0".

2
test/CodeGen/AMDGPU/verify-sop.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
# CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32

4
test/CodeGen/ARM/codemodel.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY
; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL
; RUN: not llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY
; RUN: not llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL
; TINY: Target does not support the tiny CodeModel
; KERNEL: Target does not support the kernel CodeModel

4
test/CodeGen/ARM/ldc2l.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l
define void @ldc2l(i8* %i) nounwind {

2
test/CodeGen/ARM/machine-verifier.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# RUN: not llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser runs the machine verifier after parsing.
--- |

4
test/CodeGen/ARM/named-reg-alloc.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
define i32 @get_stack() nounwind {
entry:

4
test/CodeGen/ARM/named-reg-notareg.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
define i32 @get_stack() nounwind {
entry:

2
test/CodeGen/ARM/special-reg-acore.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
; MCORE: LLVM ERROR: Invalid register name "cpsr".

4
test/CodeGen/ARM/special-reg-mcore.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 --show-mc-encoding 2>&1 | FileCheck %s --check-prefix=MCORE
; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE
; RUN: not --crash llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE
; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
; ACORE: LLVM ERROR: Invalid register name "control".
; M3CORE: LLVM ERROR: Invalid register name "xpsr_nzcvqg".

2
test/CodeGen/ARM/special-reg-v8m-base.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M
; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M
; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s
; V7M: LLVM ERROR: Invalid register name "sp_ns".

2
test/CodeGen/ARM/special-reg-v8m-main.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE
; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE
; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE
; BASELINE: LLVM ERROR: Invalid register name "faultmask_ns".

4
test/CodeGen/ARM/ssat-lower.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; immediate argument < lower-bound
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat

4
test/CodeGen/ARM/ssat-upper.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; immediate argument > upper-bound
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat

2
test/CodeGen/ARM/ssat-v4t.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s
; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s
; CHECK: Cannot select: intrinsic %llvm.arm.ssat
define i32 @ssat() nounwind {

4
test/CodeGen/ARM/stc2.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.stc2
define void @stc2(i8* %i) nounwind {

4
test/CodeGen/ARM/usat-lower.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; immediate argument < lower-bound
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat

4
test/CodeGen/ARM/usat-upper.ll
View File

@ -1,5 +1,5 @@
; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
; immediate argument > upper-bound
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat

2
test/CodeGen/ARM/usat-v4t.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s
; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat
define i32 @usat1() nounwind {

2
test/CodeGen/BPF/sdiv_error.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=bpf < %s 2> %t1
; RUN: not llc -march=bpf < %s 2> %t1
; RUN: FileCheck %s < %t1
; CHECK: Unsupport signed division

8
test/CodeGen/BPF/xadd.ll
View File

@ -1,7 +1,7 @@
; RUN: not --crash llc -march=bpfel < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=bpfeb < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=bpfel < %s 2>&1 | FileCheck %s
; RUN: not llc -march=bpfeb < %s 2>&1 | FileCheck %s
; RUN: not llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck %s
; This file is generated with the source command and source
; $ clang -target bpf -O2 -g -S -emit-llvm t.c

2
test/CodeGen/Generic/llc-start-stop-instance-errors.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \
; RUN: not llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \
; RUN: | FileCheck -check-prefix=NOT-NUM %s
; NOT-NUM: LLVM ERROR: invalid pass instance specifier dead-mi-elimination,arst

12
test/CodeGen/Generic/llc-start-stop.ll
View File

@ -23,16 +23,16 @@
; START-BEFORE: Loop Strength Reduction
; START-BEFORE-NEXT: Basic Alias Analysis (stateless AA impl)
; RUN: not --crash llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE
; RUN: not --crash llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE
; RUN: not --crash llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER
; RUN: not --crash llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER
; RUN: not llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE
; RUN: not llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE
; RUN: not llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER
; RUN: not llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER
; NONEXISTENT-START-BEFORE: "nonexistent" pass is not registered.
; NONEXISTENT-STOP-BEFORE: "nonexistent" pass is not registered.
; NONEXISTENT-START-AFTER: "nonexistent" pass is not registered.
; NONEXISTENT-STOP-AFTER: "nonexistent" pass is not registered.
; RUN: not --crash llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START
; RUN: not --crash llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP
; RUN: not llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START
; RUN: not llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP
; DOUBLE-START: start-before and start-after specified!
; DOUBLE-STOP: stop-before and stop-after specified!

2
test/CodeGen/Generic/opt-codegen-no-target-machine.ll
View File

@ -1,3 +1,3 @@
; RUN: not --crash opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s
; RUN: not opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s
; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set?

2
test/CodeGen/Hexagon/misaligned-const-load.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=hexagon < %s 2>&1 | FileCheck %s
; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s
; Check that the misaligned load is diagnosed.
; CHECK: LLVM ERROR: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-load.c:2:10

2
test/CodeGen/Hexagon/misaligned-const-store.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=hexagon < %s 2>&1 | FileCheck %s
; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s
; Check that the misaligned store is diagnosed.
; CHECK: LLVM ERROR: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-store.c:2:10

4
test/CodeGen/Hexagon/verify-liveness-at-def.mir
View File

@ -1,8 +1,8 @@
# Using a trick to run simple-register-coalescing twice, that way
# liveintervals should be preserved while running the machine verifier.
#
# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
# RUN: not llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
# RUN: not llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
---
name: test_pass

4
test/CodeGen/Lanai/codemodel.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -march=lanai < %s | FileCheck %s
; RUN: llc -march=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
; RUN: not --crash llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s
; RUN: not --crash llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s
; RUN: not llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s
; RUN: not llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s
; CHECK-TINY: Target does not support the tiny CodeModel
; CHECK-KERNEL: Target does not support the kernel CodeModel

2
test/CodeGen/MIR/X86/machine-verifier.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser runs the machine verifier after parsing.
--- |

2
test/CodeGen/MIR/X86/tied-physical-regs-match.mir
View File

@ -1,4 +1,4 @@
# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the Machine Verifier detects tied physical registers
# that doesn't match.

2
test/CodeGen/Mips/Fast-ISel/double-arg.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \
; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \
; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s
; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently

2
test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
View File

@ -1,4 +1,4 @@
; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \
; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \
; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s
; Test that FastISel aborts instead of trying to lower arguments for soft-float.

14
test/CodeGen/Mips/cpus-no-mips64.ll
View File

@ -1,13 +1,13 @@
; Check that we reject 64-bit mode on 32-bit only CPUs.
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips1 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips2 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips1 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips2 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r2 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r3 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r5 2>&1 | FileCheck %s
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r6 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r2 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r3 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r5 2>&1 | FileCheck %s
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r6 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it!

4
test/CodeGen/Mips/cpus.ll
View File

@ -57,9 +57,9 @@
; Check that we reject CPUs that are not implemented.
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \
; RUN: not llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \
; RUN: | FileCheck %s --check-prefix=ERROR
; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \
; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \
; RUN: | FileCheck %s --check-prefix=ERROR
; ERROR: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented

6
test/CodeGen/Mips/fp64a.ll
View File

@ -7,16 +7,16 @@
; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit
; FPU) on a 32-bit architecture was added in MIPS32r2.
; RUN: not --crash llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64
; RUN: not llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A
; RUN: not --crash llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A
; RUN: not --crash llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
; 32R1-FP64: LLVM ERROR: FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater.
; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI.

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