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Use correct loads for vector types during extending-load operations.
Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. llvm-svn: 161748
This commit is contained in:
Tim Northover
parent
4fc08044be
commit
b1f8be6cbe
@ -5597,26 +5597,27 @@ def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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// Vector lengthening move with load, matching extending loads.
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// extload, zextload and sextload for a standard lengthening load. Example:
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// Lengthen_Single<"8", "i16", "i8"> =
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// Pat<(v8i16 (extloadvi8 addrmode6oneL32:$addr))
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// (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (f64 (IMPLICIT_DEF)), (i32 0)))>;
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// Lengthen_Single<"8", "i16", "8"> =
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// Pat<(v8i16 (extloadvi8 addrmode6:$addr))
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// (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
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// (f64 (IMPLICIT_DEF)), (i32 0)))>;
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multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
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let AddedComplexity = 10 in {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
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(!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0)))>;
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(!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
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(!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0)))>;
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(!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
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(!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
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(VLD1LNd32 addrmode6oneL32:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0)))>;
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(!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
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}
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}
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// extload, zextload and sextload for a lengthening load which only uses
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@ -5648,8 +5649,8 @@ multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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// extload, zextload and sextload for a lengthening load followed by another
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// lengthening load, to quadruple the initial length.
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//
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
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// Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (f64 (IMPLICIT_DEF)),
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@ -5663,19 +5664,19 @@ multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0))>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0))>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0))>;
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}
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@ -5684,9 +5685,9 @@ multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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// requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
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//
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// Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// Pat<(v2i32 (extloadvi8 addrmode6:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
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// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
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// (f64 (IMPLICIT_DEF)), (i32 0))),
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// dsub_0)),
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// dsub_0)>;
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@ -5694,34 +5695,33 @@ multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn2Ty> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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(VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)),
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dsub_0)>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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(VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)),
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dsub_0)>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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(VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
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dsub_0)),
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dsub_0)>;
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}
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defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
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defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32
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defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64
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defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
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defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
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defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
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defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
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defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
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defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
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// Double lengthening - v4i8 -> v4i16 -> v4i32
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@ -5732,17 +5732,17 @@ defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
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defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
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// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
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def : Pat<(v2i64 (extloadvi8 addrmode6oneL32:$addr)),
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def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
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(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
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(VLD1LNd32 addrmode6oneL32:$addr,
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(VLD1LNd16 addrmode6:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (zextloadvi8 addrmode6oneL32:$addr)),
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def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
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(VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
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(VLD1LNd32 addrmode6oneL32:$addr,
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(VLD1LNd16 addrmode6:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
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def : Pat<(v2i64 (sextloadvi8 addrmode6oneL32:$addr)),
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def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
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(VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
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(VLD1LNd32 addrmode6oneL32:$addr,
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(VLD1LNd16 addrmode6:$addr,
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(f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
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//===----------------------------------------------------------------------===//
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