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[AVX512] Allow avx2 and sse41 nontemporal load intrinsics to select EVEX encoded instructions when VLX is enabled.

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llvm-svn: 271988
This commit is contained in:
Craig Topper 2016-06-07 07:27:57 +00:00
parent 9126a71b21
commit b20bc0d4cb
2 changed files with 13 additions and 11 deletions
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20
lib/Target/X86/X86InstrAVX512.td
View File

@ -3252,18 +3252,20 @@ let SchedRW = [WriteLoad] in {
SSEPackedInt>, EVEX, T8PD, EVEX_V512,
EVEX_CD8<64, CD8VF>;
let Predicates = [HasAVX512, HasVLX] in {
let Predicates = [HasVLX] in {
def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
(ins i256mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}", [],
SSEPackedInt>, EVEX, T8PD, EVEX_V256,
EVEX_CD8<64, CD8VF>;
(ins i256mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}",
[(set VR256X:$dst, (int_x86_avx2_movntdqa addr:$src))],
SSEPackedInt>, EVEX, T8PD, EVEX_V256,
EVEX_CD8<64, CD8VF>;
def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
(ins i128mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}", [],
SSEPackedInt>, EVEX, T8PD, EVEX_V128,
EVEX_CD8<64, CD8VF>;
(ins i128mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}",
[(set VR128X:$dst, (int_x86_sse41_movntdqa addr:$src))],
SSEPackedInt>, EVEX, T8PD, EVEX_V128,
EVEX_CD8<64, CD8VF>;
}
}

4
lib/Target/X86/X86InstrSSE.td
View File

@ -7246,12 +7246,12 @@ let Predicates = [UseSSE41] in {
}
let SchedRW = [WriteLoad] in {
let Predicates = [HasAVX] in
let Predicates = [HasAVX, NoVLX] in
def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
VEX;
let Predicates = [HasAVX2] in
let Predicates = [HasAVX2, NoVLX] in
def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}",
[(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,