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[NFC] Use SelectionDAG::getMemBasePlusOffset() instead of getNode(ISD::ADD)
Summary: To find potential opportunities to use getMemBasePlusOffset() I looked at all ISD::ADD uses found with the regex getNode\(ISD::ADD,.+,.+Ptr in lib/CodeGen/SelectionDAG. If this patch is accepted I will convert the files in the individual backends too. The motivation for this change is our out-of-tree CHERI backend (https://github.com/CTSRD-CHERI/llvm-project). We use a separate register type to store pointers (128-bit capabilities, which are effectively unforgeable and monotonic fat pointers). These capabilities permit a reduced set of operations and therefore use a separate ValueType (iFATPTR). to represent pointers implemented as capabilities. Therefore, we need to avoid using ISD::ADD for our patterns that operate on pointers and need to use a function that chooses ISD::ADD or a new ISD::PTRADD opcode depending on the value type. We originally added a new DAG.getPointerAdd() function, but after this patch series we can modify the implementation of getMemBasePlusOffset() instead. Avoiding direct uses of ISD::ADD for pointer types will significantly reduce the amount of assertion/instruction selection failures for us in future upstream merges. Reviewers: spatel Reviewed By: spatel Subscribers: merge_guards_bot, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71207
This commit is contained in:
Alex Richardson
parent
047493f270
commit
b2129c438f
@ -9295,8 +9295,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
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LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT, Align,
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LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
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BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
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DAG.getConstant(Stride, DL, BasePtr.getValueType()));
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BasePtr = DAG.getMemBasePlusOffset(BasePtr, Stride, DL);
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Loads.push_back(SplitLoad.getValue(0));
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Chains.push_back(SplitLoad.getValue(1));
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@ -10476,17 +10475,14 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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if (DAG.getDataLayout().isBigEndian())
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ShAmt = AdjustBigEndianShift(ShAmt);
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EVT PtrType = N0.getOperand(1).getValueType();
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uint64_t PtrOff = ShAmt / 8;
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unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
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SDLoc DL(LN0);
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// The original load itself didn't wrap, so an offset within it doesn't.
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(true);
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SDValue NewPtr = DAG.getNode(ISD::ADD, DL,
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PtrType, LN0->getBasePtr(),
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DAG.getConstant(PtrOff, DL, PtrType),
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Flags);
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SDValue NewPtr =
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DAG.getMemBasePlusOffset(LN0->getBasePtr(), PtrOff, DL, Flags);
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AddToWorklist(NewPtr.getNode());
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SDValue Load;
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@ -15036,8 +15032,7 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
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SDValue Ptr = St->getBasePtr();
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if (StOffset) {
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SDLoc DL(IVal);
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Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(),
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Ptr, DAG.getConstant(StOffset, DL, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, StOffset, DL);
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NewAlign = MinAlign(NewAlign, StOffset);
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}
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@ -15148,10 +15143,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
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if (NewAlign < DAG.getDataLayout().getABITypeAlignment(NewVTTy))
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return SDValue();
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SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
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Ptr.getValueType(), Ptr,
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DAG.getConstant(PtrOff, SDLoc(LD),
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Ptr.getValueType()));
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SDValue NewPtr = DAG.getMemBasePlusOffset(Ptr, PtrOff, SDLoc(LD));
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SDValue NewLD =
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DAG.getLoad(NewVT, SDLoc(N0), LD->getChain(), NewPtr,
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LD->getPointerInfo().getWithOffset(PtrOff), NewAlign,
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@ -16328,8 +16320,7 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
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SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
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ST->getAlignment(), MMOFlags, AAInfo);
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Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
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DAG.getConstant(4, DL, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, 4, DL);
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Alignment = MinAlign(Alignment, 4U);
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SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
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ST->getPointerInfo().getWithOffset(4),
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@ -16703,9 +16694,7 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
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// Lower value store.
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SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
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ST->getAlignment(), MMOFlags, AAInfo);
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Ptr =
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DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
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DAG.getConstant(HalfValBitSize / 8, DL, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, HalfValBitSize / 8, DL);
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// Higher value store.
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SDValue St1 =
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DAG.getStore(St0, DL, Hi, Ptr,
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@ -16969,7 +16958,7 @@ SDValue DAGCombiner::scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
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// operand can't represent this new access since the offset is variable.
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MPI = MachinePointerInfo(OriginalLoad->getPointerInfo().getAddrSpace());
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}
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NewPtr = DAG.getNode(ISD::ADD, DL, PtrType, NewPtr, Offset);
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NewPtr = DAG.getMemBasePlusOffset(NewPtr, Offset, DL);
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// The replacement we need to do here is a little tricky: we need to
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// replace an extractelement of a load with a load.
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@ -470,8 +470,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
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MMOFlags, AAInfo);
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(4, dl, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, 4, dl);
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Hi = DAG.getStore(Chain, dl, Hi, Ptr,
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ST->getPointerInfo().getWithOffset(4),
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MinAlign(Alignment, 4U), MMOFlags, AAInfo);
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@ -581,9 +580,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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// Store the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, dl,
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Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Hi = DAG.getNode(
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ISD::SRL, dl, Value.getValueType(), Value,
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DAG.getConstant(RoundWidth, dl,
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@ -797,9 +794,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, dl,
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Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
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@ -828,9 +823,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, dl,
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Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
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@ -1418,7 +1411,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
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unsigned Offset = TypeByteSize*i;
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SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
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Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
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Idx = DAG.getMemBasePlusOffset(FIPtr, Idx, dl);
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// If the destination vector element type is narrower than the source
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// element type, only store the bits necessary.
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@ -1481,8 +1474,7 @@ void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
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} else {
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// Advance the pointer so that the loaded byte will contain the sign bit.
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unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
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IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
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DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
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IntPtr = DAG.getMemBasePlusOffset(StackPtr, ByteOffset, DL);
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State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
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ByteOffset);
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}
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@ -2757,8 +2757,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
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// Increment the pointer to the other half.
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unsigned IncrementSize = NVT.getSizeInBits()/8;
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
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N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
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MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
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@ -2782,8 +2781,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
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Alignment, MMOFlags, AAInfo);
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// Increment the pointer to the other half.
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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// Load the rest of the low bits.
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
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N->getPointerInfo().getWithOffset(IncrementSize),
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@ -4103,8 +4101,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
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SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
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Zero, Four);
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unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
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FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
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FudgePtr, Offset);
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FudgePtr = DAG.getMemBasePlusOffset(FudgePtr, Offset, dl);
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Alignment = std::min(Alignment, 4u);
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// Load the value out, extending it from f32 to the destination float type.
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@ -169,9 +169,7 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
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// Increment the pointer to the other half.
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unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
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StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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DAG.getConstant(IncrementSize, dl,
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StackPtr.getValueType()));
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StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
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// Load the second half from the stack slot.
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Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr,
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@ -263,8 +261,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
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// Increment the pointer to the other half.
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unsigned IncrementSize = NVT.getSizeInBits() / 8;
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
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Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
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Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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MinAlign(Alignment, IncrementSize),
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@ -1164,9 +1164,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
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// Increment the pointer to the other part.
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unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
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StackPtr =
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DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
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StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
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// Load the Hi part from the stack slot.
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Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
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@ -4224,7 +4224,6 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
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SDValue Root = getRoot();
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SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
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SDLoc dl = getCurSDLoc();
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EVT PtrVT = Ptr.getValueType();
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unsigned Alignment = I.getAlignment();
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AAMDNodes AAInfo;
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I.getAAMetadata(AAInfo);
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@ -4250,8 +4249,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
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Root = Chain;
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ChainI = 0;
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}
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SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
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DAG.getConstant(Offsets[i], dl, PtrVT), Flags);
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SDValue Add = DAG.getMemBasePlusOffset(Ptr, Offsets[i], dl, Flags);
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SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
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if (MemVTs[i] != ValueVTs[i])
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Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
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@ -6695,7 +6693,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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// Add the offset to the FP.
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Value *FP = I.getArgOperand(1);
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SDValue FPVal = getValue(FP);
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SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
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SDValue Add = DAG.getMemBasePlusOffset(FPVal, OffsetVal, sdl);
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setValue(&I, Add);
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return;
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@ -3282,11 +3282,9 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
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if (newVT.isRound() &&
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shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
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EVT PtrType = Lod->getOperand(1).getValueType();
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SDValue Ptr = Lod->getBasePtr();
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if (bestOffset != 0)
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Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
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DAG.getConstant(bestOffset, dl, PtrType));
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Ptr = DAG.getMemBasePlusOffset(Ptr, bestOffset, dl);
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unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
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SDValue NewLoad = DAG.getLoad(
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newVT, dl, Lod->getChain(), Ptr,
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@ -6906,7 +6904,7 @@ SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG,
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Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index,
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DAG.getConstant(EltSize, dl, IdxVT));
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return DAG.getNode(ISD::ADD, dl, IdxVT, VecPtr, Index);
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return DAG.getMemBasePlusOffset(VecPtr, Index, dl);
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}
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//===----------------------------------------------------------------------===//
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