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[x86] Begin stubbing out the AVX support in the new vector shuffle
lowering scheme. Currently, this just directly bails to the fallback path of splitting the 256-bit vector into two 128-bit vectors, operating there, and then joining the results back together. While the results are far from perfect, they are *shockingly* good for what we're doing here. I'll be layering the rest of the functionality on top of this piece by piece and updating tests as I go. Note that 256-bit vectors in this mode are still somewhat WIP. While I think the code paths that I'm adding here are clean and good-to-go, there are still a lot of 128-bit assumptions that I'll need to stomp out as I march through the functional spread here. llvm-svn: 215637
This commit is contained in:
Chandler Carruth
parent
25db0be672
commit
b216c5b9a3
@ -8334,6 +8334,91 @@ static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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}
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}
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/// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
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/// shuffles.
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///
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/// There is a severely limited set of shuffles available in AVX1 for 256-bit
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/// vectors resulting in routinely needing to split the shuffle into two 128-bit
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/// shuffles. This can be done generically for any 256-bit vector shuffle and so
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/// we encode the logic here for specific shuffle lowering routines to bail to
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/// when they exhaust the features avaible to more directly handle the shuffle.
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static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
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SDValue V2,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDLoc DL(Op);
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MVT VT = Op.getSimpleValueType();
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assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
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assert(V1.getSimpleValueType() == VT && "Bad operand type!");
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assert(V2.getSimpleValueType() == VT && "Bad operand type!");
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
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ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
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int NumElements = VT.getVectorNumElements();
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int SplitNumElements = NumElements / 2;
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MVT ScalarVT = VT.getScalarType();
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MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
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SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
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DAG.getIntPtrConstant(0));
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SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
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DAG.getIntPtrConstant(SplitNumElements));
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SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
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DAG.getIntPtrConstant(0));
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SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
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DAG.getIntPtrConstant(SplitNumElements));
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// Now create two 4-way blends of these half-width vectors.
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auto HalfBlend = [&](ArrayRef<int> HalfMask) {
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SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
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for (int i = 0; i < SplitNumElements; ++i) {
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int M = HalfMask[i];
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if (M >= NumElements) {
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V2BlendMask.push_back(M - NumElements);
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V1BlendMask.push_back(-1);
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BlendMask.push_back(SplitNumElements + i);
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} else if (M >= 0) {
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V2BlendMask.push_back(-1);
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V1BlendMask.push_back(M);
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BlendMask.push_back(i);
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} else {
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V2BlendMask.push_back(-1);
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V1BlendMask.push_back(-1);
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BlendMask.push_back(-1);
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}
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}
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SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
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SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
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return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
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};
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SDValue Lo = HalfBlend(LoMask);
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SDValue Hi = HalfBlend(HiMask);
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
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}
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/// \brief High-level routine to lower various 256-bit x86 vector shuffles.
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///
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/// This routine either breaks down the specific type of a 256-bit x86 vector
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/// shuffle or splits it into two 128-bit shuffles and fuses the results back
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/// together based on the available instructions.
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static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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MVT VT, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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// FIXME: We should detect symmetric patterns and re-use the 128-bit shuffle
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// lowering logic with wider types in that case.
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// FIXME: We should detect when we can use AVX2 cross-half shuffles to either
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// implement the shuffle completely, more effectively build symmetry, or
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// minimize half-blends.
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// Fall back to the basic pattern of extracting the high half and forming
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// a 4-way blend.
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return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
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}
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/// \brief Tiny helper function to test whether a shuffle mask could be
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/// simplified by widening the elements being shuffled.
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static bool canWidenShuffleElements(ArrayRef<int> Mask) {
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@ -8437,6 +8522,9 @@ static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
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if (VT.getSizeInBits() == 128)
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return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
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if (VT.getSizeInBits() == 256)
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return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
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llvm_unreachable("Unimplemented!");
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}
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258
test/CodeGen/X86/vector-shuffle-256-v4.ll
Normal file
258
test/CodeGen/X86/vector-shuffle-256-v4.ll
Normal file
@ -0,0 +1,258 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=AVX1
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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define <4 x i64> @shuffle_v4i64_0001(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0001
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; AVX1: # BB#0:
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0020(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0020
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[0],xmm0[0]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0112(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0112
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1],xmm1[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 1, i32 2>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0300(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0300
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_1000(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_1000
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; AVX1: # BB#0:
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_2200(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_2200
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_3330(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_3330
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0]
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,2,3]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_3210(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_3210
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,0,1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[2,3,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0001(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0001
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; AVX1: # BB#0:
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; AVX1-NEXT: vmovlhps {{.*}} # xmm1 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0020(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0020
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[0],xmm0[0]
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; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0300(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0300
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1000(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1000
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; AVX1: # BB#0:
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1,0]
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; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_2200(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_2200
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vmovlhps {{.*}} # xmm1 = xmm1[0,0]
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; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_3330(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_3330
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0]
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; AVX1-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_3210(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_3210
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[1,0]
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[1,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0124(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0124
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm2[0],xmm1[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0142(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0142
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm2[0,1,0,1]
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[0],xmm2[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
define <4 x i64> @shuffle_v4i64_0412(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: @shuffle_v4i64_0412
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
|
||||
; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
define <4 x i64> @shuffle_v4i64_4012(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: @shuffle_v4i64_4012
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
|
||||
; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
define <4 x i64> @shuffle_v4i64_0145(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: @shuffle_v4i64_0145
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
define <4 x i64> @shuffle_v4i64_0451(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: @shuffle_v4i64_0451
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm1[2,3,0,1]
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm2[0],xmm0[1]
|
||||
; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
define <4 x i64> @shuffle_v4i64_4501(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: @shuffle_v4i64_4501
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
define <4 x i64> @shuffle_v4i64_4015(<4 x i64> %a, <4 x i64> %b) {
|
||||
; AVX1-LABEL: @shuffle_v4i64_4015
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm0[2,3,0,1]
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm2[0],xmm1[1]
|
||||
; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user