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Generate code for llvm.uadd.with.overflow intrinsic. No conversion support yet.
llvm-svn: 59786
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@ -4109,7 +4109,18 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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return 0;
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}
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case Intrinsic::uadd_with_overflow: {
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// TODO: Convert to "ISD::UADDO" instruction.
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// Convert to "ISD::UADDO" instruction.
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SDValue Op1 = getValue(I.getOperand(1));
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SDValue Op2 = getValue(I.getOperand(2));
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MVT Ty = Op1.getValueType();
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MVT ValueVTs[] = { Ty, MVT::i1 };
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SDValue Ops[] = { Op1, Op2 };
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SDValue Result = DAG.getNode(ISD::UADDO, DAG.getVTList(&ValueVTs[0], 2),
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&Ops[0], 2);
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setValue(&I, Result);
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return 0;
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}
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