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Use uint64_t as the type for the X86 TSFlag format enum. Allows removal of the VEXShift hack that was used to access the higher bits of TSFlags.
llvm-svn: 221673
This commit is contained in:
Craig Topper
parent
cd941e090d
commit
b267ba2986
@ -216,7 +216,7 @@ namespace X86II {
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MO_SECREL
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};
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enum {
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enum : uint64_t {
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//===------------------------------------------------------------------===//
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// Instruction encodings. These are the standard/most common forms for X86
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// instructions.
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@ -328,8 +328,8 @@ namespace X86II {
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OpSizeShift = 7,
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OpSizeMask = 0x3 << OpSizeShift,
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OpSize16 = 1,
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OpSize32 = 2,
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OpSize16 = 1 << OpSizeShift,
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OpSize32 = 2 << OpSizeShift,
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// which most often indicates that the instruction address 16 bit address
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@ -455,51 +455,53 @@ namespace X86II {
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EncodingMask = 0x3 << EncodingShift,
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// VEX - encoding using 0xC4/0xC5
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VEX = 1,
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VEX = 1 << EncodingShift,
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/// XOP - Opcode prefix used by XOP instructions.
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XOP = 2,
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XOP = 2 << EncodingShift,
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// VEX_EVEX - Specifies that this instruction use EVEX form which provides
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// syntax support up to 32 512-bit register operands and up to 7 16-bit
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// mask operands as well as source operand data swizzling/memory operand
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// conversion, eviction hint, and rounding mode.
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EVEX = 3,
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EVEX = 3 << EncodingShift,
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// Opcode
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OpcodeShift = EncodingShift + 2,
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//===------------------------------------------------------------------===//
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/// VEX - The opcode prefix used by AVX instructions
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VEXShift = OpcodeShift + 8,
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/// VEX_W - Has a opcode specific functionality, but is used in the same
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/// way as REX_W is for regular SSE instructions.
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VEX_W = 1U << 0,
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VEX_WShift = OpcodeShift + 8,
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VEX_W = 1ULL << VEX_WShift,
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/// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
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/// address instructions in SSE are represented as 3 address ones in AVX
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/// and the additional register is encoded in VEX_VVVV prefix.
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VEX_4V = 1U << 1,
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VEX_4VShift = VEX_WShift + 1,
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VEX_4V = 1ULL << VEX_4VShift,
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/// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode
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/// operand 3 with VEX.vvvv.
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VEX_4VOp3 = 1U << 2,
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VEX_4VOp3Shift = VEX_4VShift + 1,
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VEX_4VOp3 = 1ULL << VEX_4VOp3Shift,
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/// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
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/// must be encoded in the i8 immediate field. This usually happens in
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/// instructions with 4 operands.
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VEX_I8IMM = 1U << 3,
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VEX_I8IMMShift = VEX_4VOp3Shift + 1,
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VEX_I8IMM = 1ULL << VEX_I8IMMShift,
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/// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
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/// instruction uses 256-bit wide registers. This is usually auto detected
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/// if a VR256 register is used, but some AVX instructions also have this
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/// field marked when using a f256 memory references.
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VEX_L = 1U << 4,
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VEX_LShift = VEX_I8IMMShift + 1,
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VEX_L = 1ULL << VEX_LShift,
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// VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
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// prefix. Usually used for scalar instructions. Needed by disassembler.
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VEX_LIG = 1U << 5,
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VEX_LIGShift = VEX_LShift + 1,
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VEX_LIG = 1ULL << VEX_LIGShift,
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// TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field
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// with following encoding:
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@ -510,20 +512,24 @@ namespace X86II {
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// this will save 1 tsflag bit
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// EVEX_K - Set if this instruction requires masking
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EVEX_K = 1U << 6,
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EVEX_KShift = VEX_LIGShift + 1,
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EVEX_K = 1ULL << EVEX_KShift,
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// EVEX_Z - Set if this instruction has EVEX.Z field set.
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EVEX_Z = 1U << 7,
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EVEX_ZShift = EVEX_KShift + 1,
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EVEX_Z = 1ULL << EVEX_ZShift,
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// EVEX_L2 - Set if this instruction has EVEX.L' field set.
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EVEX_L2 = 1U << 8,
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EVEX_L2Shift = EVEX_ZShift + 1,
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EVEX_L2 = 1ULL << EVEX_L2Shift,
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// EVEX_B - Set if this instruction has EVEX.B field set.
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EVEX_B = 1U << 9,
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EVEX_BShift = EVEX_L2Shift + 1,
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EVEX_B = 1ULL << EVEX_BShift,
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// The scaling factor for the AVX512's 8-bit compressed displacement.
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CD8_Scale_Shift = VEXShift + 10,
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CD8_Scale_Mask = 127,
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CD8_Scale_Shift = EVEX_BShift + 1,
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CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
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/// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
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/// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
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@ -532,16 +538,16 @@ namespace X86II {
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/// we handle this by storeing the classifier in the opcode field and using
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/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
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Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7,
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Has3DNow0F0FOpcode = 1U << (Has3DNow0F0FOpcodeShift - VEXShift),
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Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift,
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/// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
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/// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
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MemOp4Shift = Has3DNow0F0FOpcodeShift + 1,
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MemOp4 = 1U << (MemOp4Shift - VEXShift),
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MemOp4 = 1ULL << MemOp4Shift,
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/// Explicitly specified rounding control
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EVEX_RCShift = MemOp4Shift + 1,
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EVEX_RC = 1U << (EVEX_RCShift - VEXShift)
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EVEX_RC = 1ULL << EVEX_RCShift
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};
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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@ -643,10 +649,10 @@ namespace X86II {
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/// counted as one operand.
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///
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inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) {
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
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bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
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bool HasVEX_4V = TSFlags & X86II::VEX_4V;
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bool HasMemOp4 = TSFlags & X86II::MemOp4;
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bool HasEVEX_K = TSFlags & X86II::EVEX_K;
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switch (TSFlags & X86II::FormMask) {
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default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
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case X86II::Pseudo:
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@ -687,7 +693,7 @@ namespace X86II {
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m: {
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4V = TSFlags & X86II::VEX_4V;
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unsigned FirstMemOp = 0;
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if (HasVEX_4V)
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++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV).
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@ -185,12 +185,11 @@ static bool isDisp8(int Value) {
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/// isCDisp8 - Return true if this signed displacement fits in a 8-bit
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/// compressed dispacement field.
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static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
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assert(((TSFlags & X86II::EncodingMask) >>
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X86II::EncodingShift == X86II::EVEX) &&
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assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
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"Compressed 8-bit displacement is only valid for EVEX inst.");
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unsigned CD8_Scale =
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(TSFlags >> X86II::CD8_Scale_Shift) & X86II::CD8_Scale_Mask;
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(TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
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if (CD8_Scale == 0) {
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CValue = Value;
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return isDisp8(Value);
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@ -373,9 +372,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
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const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
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unsigned BaseReg = Base.getReg();
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unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
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X86II::EncodingShift;
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bool HasEVEX = (Encoding == X86II::EVEX);
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bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
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// Handle %rip relative addressing.
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if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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@ -593,13 +590,12 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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int MemOperand, const MCInst &MI,
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const MCInstrDesc &Desc,
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raw_ostream &OS) const {
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unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
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X86II::EncodingShift;
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bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
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bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
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bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC;
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uint64_t Encoding = TSFlags & X86II::EncodingMask;
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bool HasEVEX_K = TSFlags & X86II::EVEX_K;
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bool HasVEX_4V = TSFlags & X86II::VEX_4V;
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bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3;
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bool HasMemOp4 = TSFlags & X86II::MemOp4;
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bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
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// VEX_R: opcode externsion equivalent to REX.R in
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// 1's complement (inverted) form
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@ -680,18 +676,18 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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bool EncodeRC = false;
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
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if (TSFlags & X86II::VEX_W)
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VEX_W = 1;
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
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if (TSFlags & X86II::VEX_L)
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VEX_L = 1;
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if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
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if (TSFlags & X86II::EVEX_L2)
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EVEX_L2 = 1;
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if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
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if (HasEVEX_K && (TSFlags & X86II::EVEX_Z))
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EVEX_z = 1;
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if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
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if ((TSFlags & X86II::EVEX_B))
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EVEX_b = 1;
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switch (TSFlags & X86II::OpPrefixMask) {
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@ -1109,8 +1105,8 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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raw_ostream &OS) const {
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// Emit the operand size opcode prefix as needed.
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unsigned char OpSize = (TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift;
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if (OpSize == (is16BitMode(STI) ? X86II::OpSize32 : X86II::OpSize16))
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if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32
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: X86II::OpSize16))
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EmitByte(0x66, CurByte, OS);
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switch (TSFlags & X86II::OpPrefixMask) {
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@ -1170,19 +1166,18 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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unsigned CurByte = 0;
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// Encoding type for this instruction.
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unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
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X86II::EncodingShift;
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uint64_t Encoding = TSFlags & X86II::EncodingMask;
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// It uses the VEX.VVVV field?
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
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bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
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bool HasVEX_4V = TSFlags & X86II::VEX_4V;
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bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3;
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bool HasMemOp4 = TSFlags & X86II::MemOp4;
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const unsigned MemOp4_I8IMMOperand = 2;
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// It uses the EVEX.aaa field?
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bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
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bool HasEVEX_RC = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC);
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bool HasEVEX_K = TSFlags & X86II::EVEX_K;
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bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
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// Determine where the memory operand starts, if present.
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int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
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if (MemoryOperand != -1) MemoryOperand += CurOp;
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@ -1237,7 +1232,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
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if (TSFlags & X86II::Has3DNow0F0FOpcode)
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BaseOpcode = 0x0F; // Weird 3DNow! encoding.
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unsigned SrcRegNum = 0;
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@ -1521,7 +1516,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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while (CurOp != NumOps && NumOps - CurOp <= 2) {
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// The last source register of a 4 operand instruction in AVX is encoded
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// in bits[7:4] of a immediate byte.
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
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if (TSFlags & X86II::VEX_I8IMM) {
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const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
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: CurOp);
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++CurOp;
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@ -1547,7 +1542,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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}
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}
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if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
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if (TSFlags & X86II::Has3DNow0F0FOpcode)
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EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
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#ifndef NDEBUG
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