RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

[Hexagon] Eliminate Insert4 pseudo-instruction, use combines instead

Browse Source 
llvm-svn: 286368
This commit is contained in:
Krzysztof Parzyszek 2016-11-09 14:16:29 +00:00
parent 207f5656b8
commit b28daffca5
4 changed files with 7 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1196,48 +1196,6 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MRI.clearKillFlags(Src3SubLo);
return true;
}
case Hexagon::Insert4: {
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Src1Reg = MI.getOperand(1).getReg();
unsigned Src2Reg = MI.getOperand(2).getReg();
unsigned Src3Reg = MI.getOperand(3).getReg();
unsigned Src4Reg = MI.getOperand(4).getReg();
unsigned Src1RegIsKill = getKillRegState(MI.getOperand(1).isKill());
unsigned Src2RegIsKill = getKillRegState(MI.getOperand(2).isKill());
unsigned Src3RegIsKill = getKillRegState(MI.getOperand(3).isKill());
unsigned Src4RegIsKill = getKillRegState(MI.getOperand(4).isKill());
unsigned DstSubHi = HRI.getSubReg(DstReg, Hexagon::subreg_hireg);
unsigned DstSubLo = HRI.getSubReg(DstReg, Hexagon::subreg_loreg);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert),
HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
.addReg(DstSubLo)
.addReg(Src1Reg, Src1RegIsKill)
.addImm(16)
.addImm(0);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert),
HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
.addReg(DstSubLo)
.addReg(Src2Reg, Src2RegIsKill)
.addImm(16)
.addImm(16);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert),
HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
.addReg(DstSubHi)
.addReg(Src3Reg, Src3RegIsKill)
.addImm(16)
.addImm(0);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert),
HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
.addReg(DstSubHi)
.addReg(Src4Reg, Src4RegIsKill)
.addImm(16)
.addImm(16);
MBB.erase(MI);
MRI.clearKillFlags(DstReg);
MRI.clearKillFlags(DstSubHi);
MRI.clearKillFlags(DstSubLo);
return true;
}
case Hexagon::PS_pselect: {
const MachineOperand &Op0 = MI.getOperand(0);
const MachineOperand &Op1 = MI.getOperand(1);

5
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -2956,11 +2956,6 @@ def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
let accessSize = DoubleWordAccess in
def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
let Constraints = "@earlyclobber $dst" in
def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
IntRegs:$c, IntRegs:$d),
".error \"Should never try to emit Insert4\"", []>;
//===----------------------------------------------------------------------===//
// :raw for of boundscheck:hi:lo insns
//===----------------------------------------------------------------------===//

3
lib/Target/Hexagon/HexagonPatterns.td
View File

@ -2209,7 +2209,8 @@ def: Pat<(or (or (or (shl (i64 (zext (and I32:$b, (i32 65535)))), (i32 16)),
(i64 (zext (i32 (and I32:$a, (i32 65535)))))),
(shl (i64 (anyext (and I32:$c, (i32 65535)))), (i32 32))),
(shl (Aext64 I32:$d), (i32 48))),
(Insert4 IntRegs:$a, IntRegs:$b, IntRegs:$c, IntRegs:$d)>;
(A2_combinew (A2_combine_ll I32:$d, I32:$c),
(A2_combine_ll I32:$b, I32:$a))>;
// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.

10
test/CodeGen/Hexagon/insert4.ll
View File

@ -1,9 +1,9 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we are generating insert instructions.
; CHECK: insert
; CHECK: insert
; CHECK: insert
; CHECK: insert
;
; Check that we no longer generate 4 inserts.
; CHECK: combine(r{{[0-9]+}}.l, r{{[0-9]+}}.l)
; CHECK: combine(r{{[0-9]+}}.l, r{{[0-9]+}}.l)
; CHECK-NOT: insert
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"