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MIPS DSP: add support for extract-word instructions.
llvm-svn: 164749
This commit is contained in:
Akira Hatanaka
parent
74880b0bd8
commit
b2ac1bfabe
@ -23,3 +23,19 @@ def REGIMM_OPCODE : Field6<0b000001>;
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class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasDSP];
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}
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// EXTR.W sub-class format (type 1).
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class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<2> ac;
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bits<5> shift_rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = shift_rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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@ -19,6 +19,105 @@ def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
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def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
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def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
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// Mips-specific dsp nodes
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def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
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class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
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SDNode<!strconcat("MipsISD::", Opc), Prof,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
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def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
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def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
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def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
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def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
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def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
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def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
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// Instruction encoding.
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class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
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class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
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class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
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class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
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class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
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class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
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class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
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class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
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class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
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class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
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class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
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class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
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// Instruction desc.
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 1
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//===----------------------------------------------------------------------===//
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// Extr
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class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
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class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
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class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
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class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
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NoItinerary>;
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class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
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class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
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NoItinerary>;
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class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
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NoItinerary>;
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class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
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NoItinerary>;
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class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
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NoItinerary>;
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class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
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NoItinerary>;
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class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
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NoItinerary>;
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class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
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NoItinerary>;
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// Instruction defs.
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// MIPS DSP Rev 1
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def EXTP : EXTP_ENC, EXTP_DESC;
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def EXTPV : EXTPV_ENC, EXTPV_DESC;
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def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
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def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
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def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
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def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
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def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
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def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
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def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
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def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
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def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
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def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
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// Patterns.
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class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
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Pat<pattern, result>, Requires<[pred]>;
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@ -41,3 +140,23 @@ def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
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(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
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class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
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DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
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def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
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def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
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@ -868,6 +868,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
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case ISD::LOAD: return LowerLOAD(Op, DAG);
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case ISD::STORE: return LowerSTORE(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
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}
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return SDValue();
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}
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@ -2282,6 +2284,91 @@ SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
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}
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// This function expands mips intrinsic nodes which have 64-bit input operands
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// or output values.
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//
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// out64 = intrinsic-node in64
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// =>
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// lo = copy (extract-element (in64, 0))
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// hi = copy (extract-element (in64, 1))
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// mips-specific-node
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// v0 = copy lo
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// v1 = copy hi
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// out64 = merge-values (v0, v1)
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//
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static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
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unsigned Opc, bool HasI64In, bool HasI64Out) {
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DebugLoc DL = Op.getDebugLoc();
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bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
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SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
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SmallVector<SDValue, 3> Ops;
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if (HasI64In) {
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SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
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Op->getOperand(1 + HasChainIn),
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DAG.getConstant(0, MVT::i32));
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SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
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Op->getOperand(1 + HasChainIn),
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DAG.getConstant(1, MVT::i32));
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Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
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Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
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Ops.push_back(Chain);
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Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
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Ops.push_back(Chain.getValue(1));
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} else {
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Ops.push_back(Chain);
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Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
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}
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if (!HasI64Out)
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return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
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Ops.begin(), Ops.size());
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SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
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Ops.begin(), Ops.size());
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SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
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Intr.getValue(1));
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SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
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OutLo.getValue(2));
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SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
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if (!HasChainIn)
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return Out;
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SDValue Vals[] = { Out, OutHi.getValue(1) };
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return DAG.getMergeValues(Vals, 2, DL);
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}
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SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
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default:
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return SDValue();
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}
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}
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SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
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default:
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return SDValue();
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case Intrinsic::mips_extp:
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return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
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case Intrinsic::mips_extpdp:
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return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
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case Intrinsic::mips_extr_w:
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return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
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case Intrinsic::mips_extr_r_w:
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return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
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case Intrinsic::mips_extr_rs_w:
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return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
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case Intrinsic::mips_extr_s_h:
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return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
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}
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@ -202,6 +202,8 @@ namespace llvm {
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bool IsSRA) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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110
test/CodeGen/Mips/dsp-r1.ll
Normal file
110
test/CodeGen/Mips/dsp-r1.ll
Normal file
@ -0,0 +1,110 @@
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; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
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define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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; CHECK: extr.w
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%1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
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ret i32 %1
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}
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declare i32 @llvm.mips.extr.w(i64, i32) nounwind
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define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: extrv.w
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%1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
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ret i32 %1
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}
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define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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; CHECK: extr_r.w
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%1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
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ret i32 %1
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}
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declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
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define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: extrv_s.h
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%1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
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ret i32 %1
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}
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declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
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define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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; CHECK: extr_rs.w
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%1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
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ret i32 %1
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}
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declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
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define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: extrv_rs.w
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%1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)
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ret i32 %1
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}
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define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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; CHECK: extr_s.h
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%1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15)
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ret i32 %1
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}
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define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: extrv_r.w
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%1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1)
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ret i32 %1
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}
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define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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; CHECK: extp
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%1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
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ret i32 %1
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}
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declare i32 @llvm.mips.extp(i64, i32) nounwind
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define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: extpv
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%1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1)
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ret i32 %1
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}
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define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
|
||||
entry:
|
||||
; CHECK: extpdp
|
||||
|
||||
%1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.extpdp(i64, i32) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
|
||||
entry:
|
||||
; CHECK: extpdpv
|
||||
|
||||
%1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user