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Fix ARM LDR* post-indexed operand encoding.
llvm-svn: 119869
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@ -1637,13 +1637,13 @@ multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
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(ins GPR:$Rn, am3offset:$offset), IndexModePost,
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LdMiscFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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bits<10> addr;
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bits<10> offset;
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bits<4> Rn;
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let Inst{23} = addr{8}; // U bit
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let Inst{22} = addr{9}; // 1 == imm8, 0 == Rm
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let Inst{23} = offset{8}; // U bit
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let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = Rn;
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let Inst{11-8} = offset{7-4}; // imm7_4/zero
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let Inst{3-0} = offset{3-0}; // imm3_0/Rm
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}
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}
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