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https://github.com/RPCS3/llvm-mirror.git
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[RISCV] Begin to support more subvector inserts/extracts
This patch adds support for INSERT_SUBVECTOR and EXTRACT_SUBVECTOR (nominally where both operands are scalable vector types) where the vector, subvector, and index align sufficiently to allow decomposition to subregister manipulation: * For extracts, the extracted subvector must correctly align with the lower elements of a vector register. * For inserts, the inserted subvector must be at least one full vector register, and correctly align as above. This approach should work for fixed-length vector insertion/extraction too, but that will come later. Reviewed By: craig.topper, khchen, arcbbb Differential Revision: https://reviews.llvm.org/D96873
This commit is contained in:
Fraser Cormack
parent
0099d58a88
commit
b2ba90aa15
@ -382,6 +382,48 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned IntNo,
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ReplaceNode(Node, Store);
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}
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static unsigned getRegClassIDForVecVT(MVT VT) {
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if (VT.getVectorElementType() == MVT::i1)
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return RISCV::VRRegClassID;
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return getRegClassIDForLMUL(getLMUL(VT));
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}
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// Attempt to decompose a subvector insert/extract between VecVT and
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// SubVecVT via subregister indices. Returns the subregister index that
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// can perform the subvector insert/extract with the given element index, as
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// well as the index corresponding to any leftover subvectors that must be
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// further inserted/extracted within the register class for SubVecVT.
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static std::pair<unsigned, unsigned>
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decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
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unsigned InsertExtractIdx,
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const RISCVRegisterInfo *TRI) {
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static_assert((RISCV::VRM8RegClassID > RISCV::VRM4RegClassID &&
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RISCV::VRM4RegClassID > RISCV::VRM2RegClassID &&
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RISCV::VRM2RegClassID > RISCV::VRRegClassID),
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"Register classes not ordered");
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unsigned VecRegClassID = getRegClassIDForVecVT(VecVT);
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unsigned SubRegClassID = getRegClassIDForVecVT(SubVecVT);
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// Try to compose a subregister index that takes us from the incoming
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// LMUL>1 register class down to the outgoing one. At each step we half
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// the LMUL:
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// nxv16i32@12 -> nxv2i32: sub_vrm4_1_then_sub_vrm2_1_then_sub_vrm1_0
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// Note that this is not guaranteed to find a subregister index, such as
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// when we are extracting from one VR type to another.
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unsigned SubRegIdx = RISCV::NoSubRegister;
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for (const unsigned RCID :
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{RISCV::VRM4RegClassID, RISCV::VRM2RegClassID, RISCV::VRRegClassID})
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if (VecRegClassID > RCID && SubRegClassID <= RCID) {
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VecVT = VecVT.getHalfNumVectorElementsVT();
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bool IsHi =
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InsertExtractIdx >= VecVT.getVectorElementCount().getKnownMinValue();
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SubRegIdx = TRI->composeSubRegIndices(SubRegIdx,
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getSubregIndexByMVT(VecVT, IsHi));
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if (IsHi)
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InsertExtractIdx -= VecVT.getVectorElementCount().getKnownMinValue();
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}
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return {SubRegIdx, InsertExtractIdx};
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}
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void RISCVDAGToDAGISel::Select(SDNode *Node) {
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// If we have a custom node, we have already selected.
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if (Node->isMachineOpcode()) {
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@ -704,56 +746,127 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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break;
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}
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case ISD::INSERT_SUBVECTOR: {
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// Bail when not a "cast" like insert_subvector.
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if (Node->getConstantOperandVal(2) != 0)
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break;
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if (!Node->getOperand(0).isUndef())
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break;
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SDValue V = Node->getOperand(0);
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SDValue SubV = Node->getOperand(1);
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SDLoc DL(SubV);
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auto Idx = Node->getConstantOperandVal(2);
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MVT SubVecVT = Node->getOperand(1).getSimpleValueType();
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// Bail when normal isel should do the job.
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MVT InVT = Node->getOperand(1).getSimpleValueType();
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if (VT.isFixedLengthVector() || InVT.isScalableVector())
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break;
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// TODO: This method of selecting INSERT_SUBVECTOR should work
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// with any type of insertion (fixed <-> scalable) but we don't yet
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// correctly identify the canonical register class for fixed-length types.
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// For now, keep the two paths separate.
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if (VT.isScalableVector() && SubVecVT.isScalableVector()) {
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bool IsFullVecReg = false;
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switch (getLMUL(SubVecVT)) {
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default:
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break;
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case RISCVVLMUL::LMUL_1:
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case RISCVVLMUL::LMUL_2:
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case RISCVVLMUL::LMUL_4:
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case RISCVVLMUL::LMUL_8:
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IsFullVecReg = true;
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break;
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}
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unsigned RegClassID;
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if (VT.getVectorElementType() == MVT::i1)
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RegClassID = RISCV::VRRegClassID;
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else
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RegClassID = getRegClassIDForLMUL(getLMUL(VT));
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// If the subvector doesn't occupy a full vector register then we can't
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// insert it purely using subregister manipulation. We must not clobber
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// the untouched elements (say, in the upper half of the VR register).
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if (!IsFullVecReg)
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break;
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SDValue V = Node->getOperand(1);
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SDLoc DL(V);
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SDValue RC =
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CurDAG->getTargetConstant(RegClassID, DL, Subtarget->getXLenVT());
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SDNode *NewNode =
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CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
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ReplaceNode(Node, NewNode);
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return;
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const auto *TRI = Subtarget->getRegisterInfo();
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unsigned SubRegIdx;
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std::tie(SubRegIdx, Idx) =
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decomposeSubvectorInsertExtractToSubRegs(VT, SubVecVT, Idx, TRI);
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// If the Idx hasn't been completely eliminated then this is a subvector
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// extract which doesn't naturally align to a vector register. These must
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// be handled using instructions to manipulate the vector registers.
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if (Idx != 0)
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break;
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SDNode *NewNode = CurDAG->getMachineNode(
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TargetOpcode::INSERT_SUBREG, DL, VT, V, SubV,
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CurDAG->getTargetConstant(SubRegIdx, DL, Subtarget->getXLenVT()));
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return ReplaceNode(Node, NewNode);
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}
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if (VT.isScalableVector() && SubVecVT.isFixedLengthVector()) {
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// Bail when not a "cast" like insert_subvector.
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if (Idx != 0)
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break;
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if (!Node->getOperand(0).isUndef())
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break;
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unsigned RegClassID = getRegClassIDForVecVT(VT);
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SDValue RC =
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CurDAG->getTargetConstant(RegClassID, DL, Subtarget->getXLenVT());
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SDNode *NewNode = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
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DL, VT, SubV, RC);
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ReplaceNode(Node, NewNode);
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return;
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}
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break;
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}
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case ISD::EXTRACT_SUBVECTOR: {
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// Bail when not a "cast" like extract_subvector.
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if (Node->getConstantOperandVal(1) != 0)
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break;
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// Bail when normal isel can do the job.
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MVT InVT = Node->getOperand(0).getSimpleValueType();
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if (VT.isScalableVector() || InVT.isFixedLengthVector())
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break;
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unsigned RegClassID;
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if (InVT.getVectorElementType() == MVT::i1)
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RegClassID = RISCV::VRRegClassID;
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else
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RegClassID = getRegClassIDForLMUL(getLMUL(InVT));
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SDValue V = Node->getOperand(0);
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auto Idx = Node->getConstantOperandVal(1);
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MVT InVT = Node->getOperand(0).getSimpleValueType();
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SDLoc DL(V);
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SDValue RC =
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CurDAG->getTargetConstant(RegClassID, DL, Subtarget->getXLenVT());
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SDNode *NewNode =
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CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
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ReplaceNode(Node, NewNode);
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return;
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// TODO: This method of selecting EXTRACT_SUBVECTOR should work
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// with any type of extraction (fixed <-> scalable) but we don't yet
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// correctly identify the canonical register class for fixed-length types.
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// For now, keep the two paths separate.
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if (VT.isScalableVector() && InVT.isScalableVector()) {
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const auto *TRI = Subtarget->getRegisterInfo();
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unsigned SubRegIdx;
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std::tie(SubRegIdx, Idx) =
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decomposeSubvectorInsertExtractToSubRegs(InVT, VT, Idx, TRI);
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// If the Idx hasn't been completely eliminated then this is a subvector
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// extract which doesn't naturally align to a vector register. These must
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// be handled using instructions to manipulate the vector registers.
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if (Idx != 0)
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break;
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// If we haven't set a SubRegIdx, then we must be going between LMUL<=1
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// types (VR -> VR). This can be done as a copy.
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if (SubRegIdx == RISCV::NoSubRegister) {
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unsigned RegClassID = getRegClassIDForVecVT(VT);
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unsigned InRegClassID = getRegClassIDForVecVT(InVT);
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assert(RegClassID == InRegClassID &&
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RegClassID == RISCV::VRRegClassID &&
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"Unexpected subvector extraction");
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SDValue RC =
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CurDAG->getTargetConstant(InRegClassID, DL, Subtarget->getXLenVT());
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SDNode *NewNode = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
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DL, VT, V, RC);
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return ReplaceNode(Node, NewNode);
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}
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SDNode *NewNode = CurDAG->getMachineNode(
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TargetOpcode::EXTRACT_SUBREG, DL, VT, V,
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CurDAG->getTargetConstant(SubRegIdx, DL, Subtarget->getXLenVT()));
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return ReplaceNode(Node, NewNode);
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}
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if (VT.isFixedLengthVector() && InVT.isScalableVector()) {
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// Bail when not a "cast" like extract_subvector.
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if (Idx != 0)
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break;
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unsigned InRegClassID = getRegClassIDForVecVT(InVT);
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SDValue RC =
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CurDAG->getTargetConstant(InRegClassID, DL, Subtarget->getXLenVT());
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SDNode *NewNode =
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CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, VT, V, RC);
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ReplaceNode(Node, NewNode);
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return;
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}
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break;
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}
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}
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226
test/CodeGen/RISCV/rvv/extract-subvector.ll
Normal file
226
test/CodeGen/RISCV/rvv/extract-subvector.ll
Normal file
@ -0,0 +1,226 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {
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; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m4
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; CHECK-NEXT: ret
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%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {
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; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {
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; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4
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; CHECK-NEXT: ret
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%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
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ret <vscale x 2 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {
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; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2)
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ret <vscale x 2 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) {
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; CHECK-LABEL: extract_nxv8i32_nxv2i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
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ret <vscale x 2 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) {
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; CHECK-LABEL: extract_nxv8i32_nxv2i32_6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v11
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; CHECK-NEXT: ret
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%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)
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ret <vscale x 2 x i32> %c
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}
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define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m8
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; CHECK-NEXT: ret
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%c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
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ret <vscale x 8 x i32> %c
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}
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define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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%c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
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ret <vscale x 8 x i32> %c
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}
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define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m8
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; CHECK-NEXT: ret
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%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv4i32_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v8, v12
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; CHECK-NEXT: ret
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%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv4i32_12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v8, v14
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; CHECK-NEXT: ret
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%c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8
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; CHECK-NEXT: ret
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%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
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ret <vscale x 2 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
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ret <vscale x 2 x i32> %c
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}
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define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) {
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; CHECK-LABEL: extract_nxv16i32_nxv2i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
|
||||
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
|
||||
ret <vscale x 2 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv2i32_6:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v11
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6)
|
||||
ret <vscale x 2 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv2i32_8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v12
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
|
||||
ret <vscale x 2 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv2i32_10:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v13
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10)
|
||||
ret <vscale x 2 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv2i32_12:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v14
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
|
||||
ret <vscale x 2 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv2i32_14:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v15
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)
|
||||
ret <vscale x 2 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
|
||||
ret <vscale x 1 x i32> %c
|
||||
}
|
||||
|
||||
; TODO: Extracts that don't align to a vector register are not yet supported.
|
||||
; In this case we want to extract the upper half of the lowest VR subregister
|
||||
; in the LMUL group.
|
||||
; define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {
|
||||
; %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1)
|
||||
; ret <vscale x 1 x i32> %c
|
||||
; }
|
||||
|
||||
define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv16i32_nxv1i32_2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
|
||||
ret <vscale x 1 x i32> %c
|
||||
}
|
||||
|
||||
define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) {
|
||||
; CHECK-LABEL: extract_nxv2i32_nxv1i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
|
||||
ret <vscale x 1 x i32> %c
|
||||
}
|
||||
|
||||
declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 %idx)
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
|
||||
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
|
||||
|
||||
declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
|
||||
declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
|
||||
declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
|
||||
declare <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
|
||||
206
test/CodeGen/RISCV/rvv/insert-subvector.ll
Normal file
206
test/CodeGen/RISCV/rvv/insert-subvector.ll
Normal file
@ -0,0 +1,206 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv2r.v v8, v12
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv8i32_nxv4i32_4:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv2r.v v10, v12
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv8i32_nxv2i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v12
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv8i32_nxv2i32_2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v9, v12
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv8i32_nxv2i32_4:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v10, v12
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv8i32_nxv2i32_6:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v11, v12
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv8i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv4r.v v8, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 0)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv8i32_8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv4r.v v12, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 8)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv4i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv2r.v v8, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv4i32_4:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv2r.v v10, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv4i32_8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv2r.v v12, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 8)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv4i32_12:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv2r.v v14, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 12)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_0:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v8, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v9, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_4:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v10, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_6:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v11, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v12, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 8)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_10:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v13, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 10)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_12:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v14, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 12)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
|
||||
; CHECK-LABEL: insert_nxv16i32_nxv2i32_14:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vmv1r.v v15, v16
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 14)
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
; TODO: Inserts that are less than LMUL=1 are not yet supported. In this case
|
||||
; we need mask out the unaffected elements (top half of the VR %subvec
|
||||
; register)
|
||||
;define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
|
||||
; %v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0)
|
||||
; ret <vscale x 16 x i32> %v
|
||||
;}
|
||||
|
||||
; TODO: Inserts that don't align to a vector register are not yet supported.
|
||||
; In this case we want to insert the subvector into the upper half of the
|
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; lowest VR subregister in the LMUL group.
|
||||
;define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
|
||||
; %v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1)
|
||||
; ret <vscale x 16 x i32> %v
|
||||
;}
|
||||
|
||||
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32>, <vscale x 2 x i32>, i64 %idx)
|
||||
declare <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32>, <vscale x 4 x i32>, i64 %idx)
|
||||
|
||||
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32>, <vscale x 1 x i32>, i64 %idx)
|
||||
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32>, <vscale x 2 x i32>, i64 %idx)
|
||||
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64 %idx)
|
||||
declare <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32>, <vscale x 8 x i32>, i64 %idx)
|
||||
Loading…
Reference in New Issue
Block a user