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[X86] Remove alignment restrictions from load folding table for some instructions that don't have a restriction.

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Most of these are the SSE4.1 PMOVZX/PMOVSX instructions which all read less than 128-bits. The only other was PMOVUPD which by definition is an unaligned load.

llvm-svn: 287991
This commit is contained in:
Craig Topper 2016-11-27 01:52:51 +00:00
parent 6e69c55c53
commit b2d170fa15
1 changed files with 13 additions and 13 deletions
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26
lib/Target/X86/X86InstrInfo.cpp
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@ -552,7 +552,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
{ X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
{ X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
{ X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
{ X86::MOVUPDrr, X86::MOVUPDrm, 0 },
{ X86::MOVUPSrr, X86::MOVUPSrm, 0 },
{ X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm, TB_NO_REVERSE },
{ X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
@ -567,18 +567,18 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
{ X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
{ X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
{ X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
{ X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
{ X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
{ X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
{ X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
{ X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
{ X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
{ X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
{ X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
{ X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
{ X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
{ X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
{ X86::PMOVSXBDrr, X86::PMOVSXBDrm, 0 },
{ X86::PMOVSXBQrr, X86::PMOVSXBQrm, 0 },
{ X86::PMOVSXBWrr, X86::PMOVSXBWrm, 0 },
{ X86::PMOVSXDQrr, X86::PMOVSXDQrm, 0 },
{ X86::PMOVSXWDrr, X86::PMOVSXWDrm, 0 },
{ X86::PMOVSXWQrr, X86::PMOVSXWQrm, 0 },
{ X86::PMOVZXBDrr, X86::PMOVZXBDrm, 0 },
{ X86::PMOVZXBQrr, X86::PMOVZXBQrm, 0 },
{ X86::PMOVZXBWrr, X86::PMOVZXBWrm, 0 },
{ X86::PMOVZXDQrr, X86::PMOVZXDQrm, 0 },
{ X86::PMOVZXWDrr, X86::PMOVZXWDrm, 0 },
{ X86::PMOVZXWQrr, X86::PMOVZXWQrm, 0 },
{ X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
{ X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
{ X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },