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[InstCombine] Add missing testcases for srem->urem conversion. The vector version isn't currently supported. NFC

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llvm-svn: 300436
This commit is contained in:
Craig Topper 2017-04-17 01:51:21 +00:00
parent 5ca4db2709
commit b2d434acf0
1 changed files with 22 additions and 0 deletions
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22
test/Transforms/InstCombine/rem.ll
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@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
define i64 @rem_signed(i64 %x1, i64 %y2) {
@ -571,3 +572,24 @@ rem.is.unsafe:
ret i32 0
}
define i32 @test22(i32 %A) {
; CHECK-LABEL: @test22(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 2147483647
; CHECK-NEXT: [[MUL:%.*]] = urem i32 [[AND]], 2147483647
; CHECK-NEXT: ret i32 [[MUL]]
;
%and = and i32 %A, 2147483647
%mul = srem i32 %and, 2147483647
ret i32 %mul
}
define <2 x i32> @test23(<2 x i32> %A) {
; CHECK-LABEL: @test23(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: [[MUL:%.*]] = srem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <2 x i32> [[MUL]]
;
%and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
%mul = srem <2 x i32> %and, <i32 2147483647, i32 2147483647>
ret <2 x i32> %mul
}