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[VE] vaarg functions callers and callees
Summary: Isel patterns and tests for vaarg functions as callers and callees. Reviewers: arsenm, rengolin, k-ishizaka Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits Tags: #ve, #llvm Differential Revision: https://reviews.llvm.org/D73710
This commit is contained in:
Kazushi (Jam) Marukawa
Simon Moll
parent
8301fd0d00
commit
b2d7ee731b
@ -49,6 +49,19 @@ def CC_VE : CallingConv<[
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CCDelegateTo<CC_VE_C_Stack>
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]>;
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// All arguments get passed in stack for varargs function or non-prototyped
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// function.
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def CC_VE2 : CallingConv<[
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// float --> need special handling like below.
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// 0 4
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// +------+------+
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// | empty| float|
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// +------+------+
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CCIfType<[f32], CCCustom<"allocateFloat">>,
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CCAssignToStack<0, 8>
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]>;
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def RetCC_VE : CallingConv<[
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// Promote i1/i8/i16 arguments to i32.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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@ -13,6 +13,7 @@
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#include "VEISelLowering.h"
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#include "MCTargetDesc/VEMCExpr.h"
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#include "VEMachineFunctionInfo.h"
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#include "VERegisterInfo.h"
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#include "VETargetMachine.h"
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#include "llvm/ADT/StringSwitch.h"
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@ -203,7 +204,20 @@ SDValue VETargetLowering::LowerFormalArguments(
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MachinePointerInfo::getFixedStack(MF, FI)));
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}
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assert(!IsVarArg && "TODO implement var args");
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if (!IsVarArg)
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return Chain;
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// This function takes variable arguments, some of which may have been passed
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// in registers %s0-%s8.
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//
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// The va_start intrinsic needs to know the offset to the first variable
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// argument.
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// TODO: need to calculate offset correctly once we support f128.
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unsigned ArgOffset = ArgLocs.size() * 8;
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VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
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// Skip the 176 bytes of register save area.
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FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset);
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return Chain;
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}
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@ -258,7 +272,16 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// by CC_VE would be correct now.
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CCInfo.AnalyzeCallOperands(CLI.Outs, CC_VE);
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assert(!CLI.IsVarArg);
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// VE requires to use both register and stack for varargs or no-prototyped
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// functions.
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bool UseBoth = CLI.IsVarArg;
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// Analyze operands again if it is required to store BOTH.
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SmallVector<CCValAssign, 16> ArgLocs2;
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CCState CCInfo2(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
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ArgLocs2, *DAG.getContext());
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if (UseBoth)
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CCInfo2.AnalyzeCallOperands(CLI.Outs, CC_VE2);
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// Get the size of the outgoing arguments stack space requirement.
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unsigned ArgsSize = CCInfo.getNextStackOffset();
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@ -326,7 +349,9 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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continue;
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if (!UseBoth)
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continue;
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VA = ArgLocs2[i];
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}
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assert(VA.isMemLoc());
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@ -502,6 +527,15 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BlockAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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/// VAARG handling {
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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// VAARG needs to be lowered to access with 8 bytes alignment.
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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/// } VAARG handling
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// VE has no REM or DIVREM operations.
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for (MVT IntVT : MVT::integer_valuetypes()) {
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setOperationAction(ISD::UREM, IntVT, Expand);
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@ -604,6 +638,66 @@ SDValue VETargetLowering::LowerBlockAddress(SDValue Op,
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return makeAddress(Op, DAG);
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}
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SDValue VETargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
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auto PtrVT = getPointerTy(DAG.getDataLayout());
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// Need frame address to find the address of VarArgsFrameIndex.
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MF.getFrameInfo().setFrameAddressIsTaken(true);
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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SDLoc DL(Op);
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SDValue Offset =
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DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(VE::SX9, PtrVT),
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DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
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MachinePointerInfo(SV));
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}
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SDValue VETargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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SDNode *Node = Op.getNode();
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EVT VT = Node->getValueType(0);
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SDValue InChain = Node->getOperand(0);
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SDValue VAListPtr = Node->getOperand(1);
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EVT PtrVT = VAListPtr.getValueType();
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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SDLoc DL(Node);
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SDValue VAList =
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DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
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SDValue Chain = VAList.getValue(1);
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SDValue NextPtr;
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if (VT == MVT::f32) {
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// float --> need special handling like below.
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// 0 4
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// +------+------+
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// | empty| float|
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// +------+------+
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// Increment the pointer, VAList, by 8 to the next vaarg.
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NextPtr =
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DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(8, DL));
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// Then, adjust VAList.
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unsigned InternalOffset = 4;
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VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
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DAG.getConstant(InternalOffset, DL, PtrVT));
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} else {
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// Increment the pointer, VAList, by 8 to the next vaarg.
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NextPtr =
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DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(8, DL));
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}
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// Store the incremented VAList to the legalized pointer.
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InChain = DAG.getStore(Chain, DL, NextPtr, VAListPtr, MachinePointerInfo(SV));
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// Load the actual argument out of the pointer VAList.
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// We can't count on greater alignment than the word size.
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return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
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std::min(PtrVT.getSizeInBits(), VT.getSizeInBits()) / 8);
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}
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SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default:
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@ -612,6 +706,10 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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return LowerBlockAddress(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::VASTART:
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return LowerVASTART(Op, DAG);
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case ISD::VAARG:
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return LowerVAARG(Op, DAG);
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}
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}
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/// } Custom Lower
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@ -71,6 +71,8 @@ public:
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/// Custom Lower {
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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/// } Custom Lower
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@ -296,6 +296,114 @@ void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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}
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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if (MI.getOpcode() == VE::LDSri || MI.getOpcode() == VE::LDLri ||
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MI.getOpcode() == VE::LDUri) {
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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if (MI.getOpcode() == VE::STSri || MI.getOpcode() == VE::STLri ||
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MI.getOpcode() == VE::STUri) {
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if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() == 0) {
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FrameIndex = MI.getOperand(0).getIndex();
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return MI.getOperand(2).getReg();
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}
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}
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return 0;
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}
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void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == &VE::I64RegClass) {
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BuildMI(MBB, I, DL, get(VE::STSri))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO);
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} else if (RC == &VE::I32RegClass) {
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BuildMI(MBB, I, DL, get(VE::STLri))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO);
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} else if (RC == &VE::F32RegClass) {
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BuildMI(MBB, I, DL, get(VE::STUri))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO);
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} else
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report_fatal_error("Can't store this register to stack slot");
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}
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void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
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if (RC == &VE::I64RegClass) {
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BuildMI(MBB, I, DL, get(VE::LDSri), DestReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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} else if (RC == &VE::I32RegClass) {
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BuildMI(MBB, I, DL, get(VE::LDLri), DestReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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} else if (RC == &VE::F32RegClass) {
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BuildMI(MBB, I, DL, get(VE::LDUri), DestReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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} else
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report_fatal_error("Can't load this register from stack slot");
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}
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bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case VE::EXTEND_STACK: {
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@ -59,6 +59,23 @@ public:
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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/// Stack Spill & Reload {
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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/// } Stack Spill & Reload
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// Lower pseudo instructions after register allocation.
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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@ -20,12 +20,19 @@ class VEMachineFunctionInfo : public MachineFunctionInfo {
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virtual void anchor();
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private:
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/// VarArgsFrameOffset - Frame offset to start of varargs area.
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int VarArgsFrameOffset;
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/// IsLeafProc - True if the function is a leaf procedure.
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bool IsLeafProc;
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public:
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VEMachineFunctionInfo() : IsLeafProc(false) {}
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explicit VEMachineFunctionInfo(MachineFunction &MF) : IsLeafProc(false) {}
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VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}
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explicit VEMachineFunctionInfo(MachineFunction &MF)
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: VarArgsFrameOffset(0), IsLeafProc(false) {}
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int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
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void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; }
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void setLeafProc(bool rhs) { IsLeafProc = rhs; }
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bool isLeafProc() const { return IsLeafProc; }
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63
test/CodeGen/VE/va_arg.ll
Normal file
63
test/CodeGen/VE/va_arg.ll
Normal file
@ -0,0 +1,63 @@
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; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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@.str = private unnamed_addr constant [6 x i8] c"a=%d\0A\00", align 1
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@.str.1 = private unnamed_addr constant [6 x i8] c"b=%d\0A\00", align 1
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@.str.2 = private unnamed_addr constant [6 x i8] c"c=%d\0A\00", align 1
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@.str.3 = private unnamed_addr constant [6 x i8] c"d=%u\0A\00", align 1
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@.str.4 = private unnamed_addr constant [6 x i8] c"e=%u\0A\00", align 1
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@.str.5 = private unnamed_addr constant [6 x i8] c"f=%u\0A\00", align 1
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@.str.6 = private unnamed_addr constant [6 x i8] c"g=%f\0A\00", align 1
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@.str.7 = private unnamed_addr constant [6 x i8] c"h=%p\0A\00", align 1
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@.str.8 = private unnamed_addr constant [7 x i8] c"i=%ld\0A\00", align 1
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@.str.9 = private unnamed_addr constant [7 x i8] c"j=%lf\0A\00", align 1
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define i32 @func_vainout(i32, ...) {
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; CHECK-LABEL: func_vainout:
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; CHECK: ldl.sx %s1, 184(,%s9)
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; CHECK: ld2b.sx %s18, 192(,%s9)
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; CHECK: ld1b.sx %s19, 200(,%s9)
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; CHECK: ldl.sx %s20, 208(,%s9)
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; CHECK: ld2b.zx %s21, 216(,%s9)
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; CHECK: ld1b.zx %s22, 224(,%s9)
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; CHECK: ldu %s23, 236(,%s9)
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; CHECK: ld %s24, 240(,%s9)
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; CHECK: ld %s25, 248(,%s9)
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; CHECK: ld %s26, 256(,%s9)
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%a = alloca i8*, align 8
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%a8 = bitcast i8** %a to i8*
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call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %a8)
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call void @llvm.va_start(i8* nonnull %a8)
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%p0 = va_arg i8** %a, i32
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%p1 = va_arg i8** %a, i16
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%p2 = va_arg i8** %a, i8
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%p3 = va_arg i8** %a, i32
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%p4 = va_arg i8** %a, i16
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%p5 = va_arg i8** %a, i8
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%p6 = va_arg i8** %a, float
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%p7 = va_arg i8** %a, i8*
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%p8 = va_arg i8** %a, i64
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%p9 = va_arg i8** %a, double
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call void @llvm.va_end(i8* nonnull %a8)
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call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %a8)
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%pf0 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), i32 %p0)
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%p1.s32 = sext i16 %p1 to i32
|
||||
%pf1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.1, i64 0, i64 0), i32 %p1.s32)
|
||||
%p2.s32 = sext i8 %p2 to i32
|
||||
%pf2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.2, i64 0, i64 0), i32 %p2.s32)
|
||||
%pf3 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.3, i64 0, i64 0), i32 %p3)
|
||||
%p4.z32 = zext i16 %p4 to i32
|
||||
%pf4 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.4, i64 0, i64 0), i32 %p4.z32)
|
||||
%p5.z32 = zext i8 %p5 to i32
|
||||
%pf5 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.5, i64 0, i64 0), i32 %p5.z32)
|
||||
%pf6 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.6, i64 0, i64 0), float %p6)
|
||||
%pf7 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.7, i64 0, i64 0), i8* %p7)
|
||||
%pf8 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.8, i64 0, i64 0), i64 %p8)
|
||||
%pf9 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.9, i64 0, i64 0), double %p9)
|
||||
ret i32 0
|
||||
}
|
||||
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
|
||||
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
|
||||
declare void @llvm.va_start(i8*)
|
||||
declare void @llvm.va_end(i8*)
|
||||
declare i32 @printf(i8* nocapture readonly, ...)
|
||||
152
test/CodeGen/VE/va_callee.ll
Normal file
152
test/CodeGen/VE/va_callee.ll
Normal file
@ -0,0 +1,152 @@
|
||||
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
|
||||
|
||||
define i32 @va_func(i32, ...) {
|
||||
; CHECK-LABEL: va_func:
|
||||
; CHECK: ldl.sx %s0, 184(,%s9)
|
||||
; CHECK: ld2b.sx %s18, 192(,%s9)
|
||||
; CHECK: ld1b.sx %s19, 200(,%s9)
|
||||
; CHECK: ldl.sx %s20, 208(,%s9)
|
||||
; CHECK: ld2b.zx %s21, 216(,%s9)
|
||||
; CHECK: ld1b.zx %s22, 224(,%s9)
|
||||
; CHECK: ldu %s23, 236(,%s9)
|
||||
; CHECK: ld %s24, 240(,%s9)
|
||||
; CHECK: ld %s25, 248(,%s9)
|
||||
|
||||
%va = alloca i8*, align 8
|
||||
%va.i8 = bitcast i8** %va to i8*
|
||||
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_start(i8* nonnull %va.i8)
|
||||
%p1 = va_arg i8** %va, i32
|
||||
%p2 = va_arg i8** %va, i16
|
||||
%p3 = va_arg i8** %va, i8
|
||||
%p4 = va_arg i8** %va, i32
|
||||
%p5 = va_arg i8** %va, i16
|
||||
%p6 = va_arg i8** %va, i8
|
||||
%p7 = va_arg i8** %va, float
|
||||
%p8 = va_arg i8** %va, i8*
|
||||
%p9 = va_arg i8** %va, i64
|
||||
%p10 = va_arg i8** %va, double
|
||||
call void @llvm.va_end(i8* nonnull %va.i8)
|
||||
call void @use_i32(i32 %p1)
|
||||
call void @use_s16(i16 %p2)
|
||||
call void @use_s8(i8 %p3)
|
||||
call void @use_i32(i32 %p4)
|
||||
call void @use_u16(i16 %p5)
|
||||
call void @use_u8(i8 %p6)
|
||||
call void @use_float(float %p7)
|
||||
call void @use_i8p(i8* %p8)
|
||||
call void @use_i64(i64 %p9)
|
||||
call void @use_double(double %p10)
|
||||
call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @va_copy0(i32, ...) {
|
||||
; CHECK-LABEL: va_copy0:
|
||||
; CHECK: ldl.sx %s0,
|
||||
; CHECK: ld2b.sx %s18,
|
||||
; CHECK: ld1b.sx %s19,
|
||||
; CHECK: ldl.sx %s20,
|
||||
; CHECK: ld2b.zx %s21,
|
||||
; CHECK: ld1b.zx %s22,
|
||||
; CHECK: ldu %s23,
|
||||
; CHECK: ld %s24,
|
||||
; CHECK: ld %s25,
|
||||
|
||||
%va = alloca i8*, align 8
|
||||
%va.i8 = bitcast i8** %va to i8*
|
||||
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_start(i8* nonnull %va.i8)
|
||||
%vb = alloca i8*, align 8
|
||||
%vb.i8 = bitcast i8** %vb to i8*
|
||||
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_copy(i8* nonnull %vb.i8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_end(i8* nonnull %va.i8)
|
||||
call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
%p1 = va_arg i8** %vb, i32
|
||||
%p2 = va_arg i8** %vb, i16
|
||||
%p3 = va_arg i8** %vb, i8
|
||||
%p4 = va_arg i8** %vb, i32
|
||||
%p5 = va_arg i8** %vb, i16
|
||||
%p6 = va_arg i8** %vb, i8
|
||||
%p7 = va_arg i8** %vb, float
|
||||
%p8 = va_arg i8** %vb, i8*
|
||||
%p9 = va_arg i8** %vb, i64
|
||||
%p10 = va_arg i8** %vb, double
|
||||
call void @llvm.va_end(i8* nonnull %vb.i8)
|
||||
call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %vb.i8)
|
||||
call void @use_i32(i32 %p1)
|
||||
call void @use_s16(i16 %p2)
|
||||
call void @use_s8(i8 %p3)
|
||||
call void @use_i32(i32 %p4)
|
||||
call void @use_u16(i16 %p5)
|
||||
call void @use_u8(i8 %p6)
|
||||
call void @use_float(float %p7)
|
||||
call void @use_i8p(i8* %p8)
|
||||
call void @use_i64(i64 %p9)
|
||||
call void @use_double(double %p10)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i32 @va_copy8(i32, ...) {
|
||||
; CHECK-LABEL: va_copy8:
|
||||
; CHECK: ldl.sx %s0,
|
||||
; CHECK: ld2b.sx %s18,
|
||||
; CHECK: ld1b.sx %s19,
|
||||
; CHECK: ldl.sx %s20,
|
||||
; CHECK: ld2b.zx %s21,
|
||||
; CHECK: ld1b.zx %s22,
|
||||
; CHECK: ldu %s23,
|
||||
; CHECK: ld %s24,
|
||||
; CHECK: ld %s25,
|
||||
|
||||
%va = alloca i8*, align 8
|
||||
%va.i8 = bitcast i8** %va to i8*
|
||||
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_start(i8* nonnull %va.i8)
|
||||
%p1 = va_arg i8** %va, i32
|
||||
%p2 = va_arg i8** %va, i16
|
||||
%p3 = va_arg i8** %va, i8
|
||||
%p4 = va_arg i8** %va, i32
|
||||
%p5 = va_arg i8** %va, i16
|
||||
%p6 = va_arg i8** %va, i8
|
||||
%p7 = va_arg i8** %va, float
|
||||
|
||||
%vc = alloca i8*, align 8
|
||||
%vc.i8 = bitcast i8** %vc to i8*
|
||||
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_copy(i8* nonnull %vc.i8, i8* nonnull %va.i8)
|
||||
call void @llvm.va_end(i8* nonnull %va.i8)
|
||||
%p8 = va_arg i8** %vc, i8*
|
||||
%p9 = va_arg i8** %vc, i64
|
||||
%p10 = va_arg i8** %vc, double
|
||||
call void @llvm.va_end(i8* nonnull %vc.i8)
|
||||
call void @use_i32(i32 %p1)
|
||||
call void @use_s16(i16 %p2)
|
||||
call void @use_s8(i8 %p3)
|
||||
call void @use_i32(i32 %p4)
|
||||
call void @use_u16(i16 %p5)
|
||||
call void @use_u8(i8 %p6)
|
||||
call void @use_float(float %p7)
|
||||
call void @use_i8p(i8* %p8)
|
||||
call void @use_i64(i64 %p9)
|
||||
call void @use_double(double %p10)
|
||||
call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %va.i8)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
declare void @use_i64(i64)
|
||||
declare void @use_i32(i32)
|
||||
declare void @use_u16(i16 zeroext)
|
||||
declare void @use_u8(i8 zeroext)
|
||||
declare void @use_s16(i16 signext)
|
||||
declare void @use_s8(i8 signext)
|
||||
declare void @use_i8p(i8*)
|
||||
declare void @use_float(float)
|
||||
declare void @use_double(double)
|
||||
|
||||
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
|
||||
declare void @llvm.va_start(i8*)
|
||||
declare void @llvm.va_copy(i8*, i8*)
|
||||
declare void @llvm.va_end(i8*)
|
||||
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
|
||||
47
test/CodeGen/VE/va_caller.ll
Normal file
47
test/CodeGen/VE/va_caller.ll
Normal file
@ -0,0 +1,47 @@
|
||||
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
|
||||
|
||||
declare i32 @func(i32, ...)
|
||||
|
||||
define i32 @caller() {
|
||||
; CHECK-LABEL: caller:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: st %s18, 48(,%s9) # 8-byte Folded Spill
|
||||
; CHECK-NEXT: or %s7, 0, (0)1
|
||||
; CHECK-NEXT: st %s7, 280(,%s11)
|
||||
; CHECK-NEXT: or %s0, 11, (0)1
|
||||
; CHECK-NEXT: st %s0, 272(,%s11)
|
||||
; CHECK-NEXT: st %s7, 264(,%s11)
|
||||
; CHECK-NEXT: or %s0, 10, (0)1
|
||||
; CHECK-NEXT: st %s0, 256(,%s11)
|
||||
; CHECK-NEXT: lea.sl %s0, 1075970048
|
||||
; CHECK-NEXT: st %s0, 248(,%s11)
|
||||
; CHECK-NEXT: or %s0, 8, (0)1
|
||||
; CHECK-NEXT: st %s0, 240(,%s11)
|
||||
; CHECK-NEXT: st %s7, 232(,%s11)
|
||||
; CHECK-NEXT: lea %s0, 1086324736
|
||||
; CHECK-NEXT: stl %s0, 228(,%s11)
|
||||
; CHECK-NEXT: or %s5, 5, (0)1
|
||||
; CHECK-NEXT: stl %s5, 216(,%s11)
|
||||
; CHECK-NEXT: or %s4, 4, (0)1
|
||||
; CHECK-NEXT: stl %s4, 208(,%s11)
|
||||
; CHECK-NEXT: or %s3, 3, (0)1
|
||||
; CHECK-NEXT: stl %s3, 200(,%s11)
|
||||
; CHECK-NEXT: or %s2, 2, (0)1
|
||||
; CHECK-NEXT: stl %s2, 192(,%s11)
|
||||
; CHECK-NEXT: or %s1, 1, (0)1
|
||||
; CHECK-NEXT: stl %s1, 184(,%s11)
|
||||
; CHECK-NEXT: or %s18, 0, (0)1
|
||||
; CHECK-NEXT: lea %s0, func@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, func@hi(%s0)
|
||||
; CHECK-NEXT: lea.sl %s0, 1086324736
|
||||
; CHECK-NEXT: stl %s18, 176(,%s11)
|
||||
; CHECK-NEXT: or %s6, 0, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s18
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: or %s0, 0, %s18
|
||||
; CHECK-NEXT: ld %s18, 48(,%s9) # 8-byte Folded Reload
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
call i32 (i32, ...) @func(i32 0, i16 1, i8 2, i32 3, i16 4, i8 5, float 6.0, i8* null, i64 8, double 9.0, i128 10, i128 11)
|
||||
ret i32 0
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user