From b2daeac125167d2c03f1f0b05491ffc202a62ed2 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 15 Nov 2010 05:19:05 +0000 Subject: [PATCH] add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120 --- include/llvm/Target/Target.td | 3 ++ lib/Target/ARM/ARMAsmPrinter.cpp | 2 +- lib/Target/ARM/ARMInstrFormats.td | 10 +++--- lib/Target/ARM/ARMInstrInfo.td | 40 +++++++++++------------ lib/Target/ARM/ARMInstrThumb2.td | 4 +-- lib/Target/ARM/ARMMCCodeEmitter.cpp | 2 +- lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp | 2 +- lib/Target/X86/X86MCCodeEmitter.cpp | 2 +- utils/TableGen/CodeEmitterGen.cpp | 6 ++-- utils/TableGen/CodeGenInstruction.cpp | 3 +- 10 files changed, 38 insertions(+), 36 deletions(-) diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 760996e3e74..bd629f16e25 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -243,6 +243,8 @@ class Instruction { /// be encoded into the output machineinstr. string DisableEncoding = ""; + string PostEncoderMethod = ""; + /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. bits<64> TSFlags = 0; } @@ -343,6 +345,7 @@ def ImmAsmOperand : AsmOperandClass { class Operand { ValueType Type = ty; string PrintMethod = "printOperand"; + string EncoderMethod = ""; string AsmOperandLowerMethod = ?; dag MIOperandInfo = (ops); diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 3a97a6935c6..e7ac48cbcfa 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -200,7 +200,7 @@ namespace { MachineLocation getDebugValueLocation(const MachineInstr *MI) const { MachineLocation Location; - assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); + assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); // Frame address. Currently handles register +- offset only. if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index aeb2f1db1e3..774c4410ad9 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -154,13 +154,13 @@ def pred : PredicateOperand { - string EncoderMethod = "getCCOutOpValue"; + let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; } // Same as cc_out except it defaults to setting CPSR. def s_cc_out : OptionalDefOperand { - string EncoderMethod = "getCCOutOpValue"; + let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; } @@ -1675,7 +1675,7 @@ class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4, let Inst{11-8} = op11_8; let Inst{7-4} = op7_4; - string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; + let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; bits<5> Vd; bits<6> Rn; @@ -1718,7 +1718,7 @@ class NDataI { let Inst{31-25} = 0b1111001; - string PostEncoderMethod = "NEONThumb2DataIPostEncoder"; + let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; } class NDataXI opcod1, bits<4> opcod2, bits<2> opcod3, let Pattern = pattern; list Predicates = [HasNEON]; - string PostEncoderMethod = "NEONThumb2DupPostEncoder"; + let PostEncoderMethod = "NEONThumb2DupPostEncoder"; bits<5> V; bits<4> R; diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index f163c1b1bbb..3ba0cebd658 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -231,7 +231,7 @@ def bf_inv_mask_imm : Operand, PatLeaf<(imm), [{ return ARM::isBitFieldInvertedMask(N->getZExtValue()); }] > { - string EncoderMethod = "getBitfieldInvertedMaskOpValue"; + let EncoderMethod = "getBitfieldInvertedMaskOpValue"; let PrintMethod = "printBitfieldInvMaskImmOperand"; } @@ -275,13 +275,13 @@ def sube_live_carry : // Branch target. def brtarget : Operand { - string EncoderMethod = "getBranchTargetOpValue"; + let EncoderMethod = "getBranchTargetOpValue"; } // Call target. def bltarget : Operand { // Encoded the same as branch targets. - string EncoderMethod = "getBranchTargetOpValue"; + let EncoderMethod = "getBranchTargetOpValue"; } // A list of registers separated by comma. Used by load/store multiple. @@ -291,7 +291,7 @@ def RegListAsmOperand : AsmOperandClass { } def reglist : Operand { - string EncoderMethod = "getRegisterListOpValue"; + let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = RegListAsmOperand; let PrintMethod = "printRegisterList"; } @@ -314,14 +314,14 @@ def pclabel : Operand { } def neon_vcvt_imm32 : Operand { - string EncoderMethod = "getNEONVcvtImm32OpValue"; + let EncoderMethod = "getNEONVcvtImm32OpValue"; } // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. def rot_imm : Operand, PatLeaf<(i32 imm), [{ - int32_t v = (int32_t)N->getZExtValue(); - return v == 8 || v == 16 || v == 24; }]> { - string EncoderMethod = "getRotImmOpValue"; + int32_t v = (int32_t)N->getZExtValue(); + return v == 8 || v == 16 || v == 24; }]> { + let EncoderMethod = "getRotImmOpValue"; } // shift_imm: An integer that encodes a shift amount and the type of shift @@ -335,14 +335,14 @@ def shift_imm : Operand { def so_reg : Operand, // reg reg imm ComplexPattern { - string EncoderMethod = "getSORegOpValue"; + let EncoderMethod = "getSORegOpValue"; let PrintMethod = "printSORegOperand"; let MIOperandInfo = (ops GPR, GPR, i32imm); } def shift_so_reg : Operand, // reg reg imm ComplexPattern { - string EncoderMethod = "getSORegOpValue"; + let EncoderMethod = "getSORegOpValue"; let PrintMethod = "printSORegOperand"; let MIOperandInfo = (ops GPR, GPR, i32imm); } @@ -353,7 +353,7 @@ def shift_so_reg : Operand, // reg reg imm // into so_imm instructions: the 8-bit immediate is the least significant bits // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. def so_imm : Operand, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> { - string EncoderMethod = "getSOImmOpValue"; + let EncoderMethod = "getSOImmOpValue"; let PrintMethod = "printSOImmOperand"; } @@ -407,7 +407,7 @@ def imm0_31 : Operand, PatLeaf<(imm), [{ def imm0_31_m1 : Operand, PatLeaf<(imm), [{ return (int32_t)N->getZExtValue() < 32; }]> { - string EncoderMethod = "getImmMinusOneOpValue"; + let EncoderMethod = "getImmMinusOneOpValue"; } // Define ARM specific addressing modes. @@ -421,7 +421,7 @@ def addrmode_imm12 : Operand, // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other // immediate values are as normal. - string EncoderMethod = "getAddrModeImm12OpValue"; + let EncoderMethod = "getAddrModeImm12OpValue"; let PrintMethod = "printAddrModeImm12Operand"; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } @@ -429,7 +429,7 @@ def addrmode_imm12 : Operand, // def ldst_so_reg : Operand, ComplexPattern { - string EncoderMethod = "getLdStSORegOpValue"; + let EncoderMethod = "getLdStSORegOpValue"; // FIXME: Simplify the printer let PrintMethod = "printAddrMode2Operand"; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); @@ -456,7 +456,7 @@ def am2offset : Operand, // def addrmode3 : Operand, ComplexPattern { - string EncoderMethod = "getAddrMode3OpValue"; + let EncoderMethod = "getAddrMode3OpValue"; let PrintMethod = "printAddrMode3Operand"; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } @@ -464,7 +464,7 @@ def addrmode3 : Operand, def am3offset : Operand, ComplexPattern { - string EncoderMethod = "getAddrMode3OffsetOpValue"; + let EncoderMethod = "getAddrMode3OffsetOpValue"; let PrintMethod = "printAddrMode3OffsetOperand"; let MIOperandInfo = (ops GPR, i32imm); } @@ -472,7 +472,7 @@ def am3offset : Operand, // ldstm_mode := {ia, ib, da, db} // def ldstm_mode : OptionalDefOperand { - string EncoderMethod = "getLdStmModeOpValue"; + let EncoderMethod = "getLdStmModeOpValue"; let PrintMethod = "printLdStmModeOperand"; } @@ -488,7 +488,7 @@ def addrmode5 : Operand, let PrintMethod = "printAddrMode5Operand"; let MIOperandInfo = (ops GPR:$base, i32imm); let ParserMatchClass = MemMode5AsmOperand; - string EncoderMethod = "getAddrMode5OpValue"; + let EncoderMethod = "getAddrMode5OpValue"; } // addrmode6 := reg with optional writeback @@ -497,13 +497,13 @@ def addrmode6 : Operand, ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); - string EncoderMethod = "getAddrMode6AddressOpValue"; + let EncoderMethod = "getAddrMode6AddressOpValue"; } def am6offset : Operand { let PrintMethod = "printAddrMode6OffsetOperand"; let MIOperandInfo = (ops GPR); - string EncoderMethod = "getAddrMode6OffsetOpValue"; + let EncoderMethod = "getAddrMode6OffsetOpValue"; } // addrmodepc := pc + reg diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index ad017a7c548..a8de8abd76d 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -31,7 +31,7 @@ def tb_addrmode : Operand { def t2_so_reg : Operand, // reg imm ComplexPattern { - string EncoderMethod = "getT2SORegOpValue"; + let EncoderMethod = "getT2SORegOpValue"; let PrintMethod = "printT2SOOperand"; let MIOperandInfo = (ops rGPR, i32imm); } @@ -53,7 +53,7 @@ def t2_so_imm_neg_XFORM : SDNodeXForm, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> { - string EncoderMethod = "getT2SOImmOpValue"; + let EncoderMethod = "getT2SOImmOpValue"; } // t2_so_imm_not - Match an immediate that is a complement diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 0b896edef53..b156755bb50 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "arm-emitter" +#define DEBUG_TYPE "mccodeemitter" #include "ARM.h" #include "ARMAddressingModes.h" #include "ARMFixupKinds.h" diff --git a/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp b/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp index adbec06804c..19dc89b37b0 100644 --- a/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp +++ b/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "mblaze-emitter" +#define DEBUG_TYPE "mccodeemitter" #include "MBlaze.h" #include "MBlazeInstrInfo.h" #include "MBlazeFixupKinds.h" diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp index 950fdf107a2..fea37f85a74 100644 --- a/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/X86MCCodeEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "x86-emitter" +#define DEBUG_TYPE "mccodeemitter" #include "X86.h" #include "X86InstrInfo.h" #include "X86FixupKinds.h" diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index e7b022af15f..debc8776134 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -230,9 +230,9 @@ void CodeEmitterGen::run(raw_ostream &o) { } } - if (R->getValue("PostEncoderMethod")) - Case += " Value = " + - R->getValueAsString("PostEncoderMethod") + "(MI, Value);\n"; + std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); + if (!PostEmitter.empty()) + Case += " Value = " + PostEmitter + "(MI, Value);\n"; std::vector &InstList = CaseMap[Case]; InstList.push_back(InstName); diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index 84a8b9137e1..575852b1ad7 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -71,8 +71,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { if (Rec->isSubClassOf("Operand")) { PrintMethod = Rec->getValueAsString("PrintMethod"); // If there is an explicit encoder method, use it. - if (Rec->getValue("EncoderMethod")) - EncoderMethod = Rec->getValueAsString("EncoderMethod"); + EncoderMethod = Rec->getValueAsString("EncoderMethod"); MIOpInfo = Rec->getValueAsDag("MIOperandInfo"); // Verify that MIOpInfo has an 'ops' root value.