RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity

[ARM] support for Cortex-R4/R4F

Browse Source 
Currently, llvm (backend) doesn't know cortex-r4, even though it is the
default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes
'cortex-r4' is not a recognized processor for this target' by llvm.
This patch adds support for cortex-r4 and, very closely related, r4f.

llvm-svn: 234486
This commit is contained in:
Javed Absar 2015-04-09 14:07:28 +00:00
parent 4fb23cdd75
commit b2e5d643a8
5 changed files with 81 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/ARM.td
View File

@ -255,6 +255,14 @@ def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto, FeatureCRC]>;
def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
"Cortex-R4 ARM processors",
[FeatureHWDiv,
FeatureAvoidPartialCPSR,
FeatureDSPThumb2, FeatureT2XtPk,
HasV7Ops, FeatureDB, FeatureHasRAS,
FeatureRClass]>;
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors",
[FeatureSlowFPBrcc,
@ -391,6 +399,16 @@ def : ProcessorModel<"krait", CortexA9Model,
FeatureDSPThumb2, FeatureHasRAS,
FeatureAClass]>;
// FIXME: R4 has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r4", CortexA8Model,
[ProcR4]>;
// FIXME: R4F has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r4f", CortexA8Model,
[ProcR4,
FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
FeatureVFP3, FeatureVFPOnlySP, FeatureD16]>;
// FIXME: R5 has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r5", CortexA8Model,
[ProcR5, HasV7Ops, FeatureDB,

2
lib/Target/ARM/ARMSubtarget.h
View File

@ -43,7 +43,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
CortexA17, CortexR5, Swift, CortexA53, CortexA57, Krait,
CortexA17, CortexR4, CortexR4F, CortexR5, Swift, CortexA53, CortexA57, Krait,
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass

45
test/CodeGen/ARM/build-attributes.ll
View File

@ -81,6 +81,8 @@
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4 | FileCheck %s --check-prefix=CORTEX-R4
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4f | FileCheck %s --check-prefix=CORTEX-R4F
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
@ -1012,6 +1014,49 @@
; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 22
; CORTEX-M7-NOFPU-FAST: .eabi_attribute 23, 1
; CORTEX-R4: .cpu cortex-r4
; CORTEX-R4: .eabi_attribute 6, 10
; CORTEX-R4: .eabi_attribute 7, 82
; CORTEX-R4: .eabi_attribute 8, 1
; CORTEX-R4: .eabi_attribute 9, 2
; CORTEX-R4-NOT: .fpu vfpv3-d16
; CORTEX-R4-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R4: .eabi_attribute 20, 1
; CORTEX-R4: .eabi_attribute 21, 1
; CORTEX-R4-NOT: .eabi_attribute 22
; CORTEX-R4: .eabi_attribute 23, 3
; CORTEX-R4: .eabi_attribute 24, 1
; CORTEX-R4: .eabi_attribute 25, 1
; CORTEX-R4-NOT: .eabi_attribute 28
; CORTEX-R4-NOT: .eabi_attribute 36
; CORTEX-R4: .eabi_attribute 38, 1
; CORTEX-R4-NOT: .eabi_attribute 42
; CORTEX-R4-NOT: .eabi_attribute 44
; CORTEX-R4-NOT: .eabi_attribute 68
; CORTEX-R4F: .cpu cortex-r4f
; CORTEX-R4F: .eabi_attribute 6, 10
; CORTEX-R4F: .eabi_attribute 7, 82
; CORTEX-R4F: .eabi_attribute 8, 1
; CORTEX-R4F: .eabi_attribute 9, 2
; CORTEX-R4F: .fpu vfpv3-d16
; CORTEX-R4F-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R4F: .eabi_attribute 20, 1
; CORTEX-R4F: .eabi_attribute 21, 1
; CORTEX-R4F-NOT: .eabi_attribute 22
; CORTEX-R4F: .eabi_attribute 23, 3
; CORTEX-R4F: .eabi_attribute 24, 1
; CORTEX-R4F: .eabi_attribute 25, 1
; CORTEX-R4F: .eabi_attribute 27, 1
; CORTEX-R4F-NOT: .eabi_attribute 28
; CORTEX-R4F-NOT: .eabi_attribute 36
; CORTEX-R4F: .eabi_attribute 38, 1
; CORTEX-R4F-NOT: .eabi_attribute 42
; CORTEX-R4F-NOT: .eabi_attribute 44
; CORTEX-R4F-NOT: .eabi_attribute 68
; CORTEX-R5: .cpu cortex-r5
; CORTEX-R5: .eabi_attribute 6, 10
; CORTEX-R5: .eabi_attribute 7, 82

24
test/CodeGen/ARM/div.ll
View File

@ -1,11 +1,13 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
define i32 @f1(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f1
; CHECK-ARM: __divsi3
; CHECK-SWDIV: f1
; CHECK-SWDIV: __divsi3
; CHECK-HWDIV: f1
; CHECK-HWDIV: sdiv
@ -15,8 +17,8 @@ entry:
define i32 @f2(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f2
; CHECK-ARM: __udivsi3
; CHECK-SWDIV: f2
; CHECK-SWDIV: __udivsi3
; CHECK-HWDIV: f2
; CHECK-HWDIV: udiv
@ -26,8 +28,8 @@ entry:
define i32 @f3(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f3
; CHECK-ARM: __modsi3
; CHECK-SWDIV: f3
; CHECK-SWDIV: __modsi3
; CHECK-HWDIV: f3
; CHECK-HWDIV: sdiv
@ -38,8 +40,8 @@ entry:
define i32 @f4(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f4
; CHECK-ARM: __umodsi3
; CHECK-SWDIV: f4
; CHECK-SWDIV: __umodsi3
; CHECK-HWDIV: f4
; CHECK-HWDIV: udiv

4
test/CodeGen/Thumb2/div.ll
View File

@ -4,6 +4,10 @@
; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M
; RUN: llc -mtriple=thumb-apple-darwin -mcpu=swift %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r4 %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r4f %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r5 %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV