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[X86] Teach the backend how to fold target specific dag node for packed
vector shift by immedate count (VSHLI/VSRLI/VSRAI) into a build_vector when the vector in input to the shift is a build_vector of all constants or UNDEFs. Target specific nodes for packed shifts by immediate count are in general introduced by function 'getTargetVShiftByConstNode' (in X86ISelLowering.cpp) when lowering shift operations, SSE/AVX immediate shift intrinsics and (only in very few cases) SIGN_EXTEND_INREG dag nodes. This patch adds extra rules for simplifying vector shifts inside function 'getTargetVShiftByConstNode'. Added file test/CodeGen/X86/vec_shift5.ll to verify that packed shifts by immediate are correctly folded into a build_vector when the input vector to the shift dag node is a vector of constants or undefs. llvm-svn: 198113
This commit is contained in:
Andrea Di Biagio
parent
e4373d751b
commit
b2f4969e98
@ -11103,11 +11103,12 @@ static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
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static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
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SDValue SrcOp, uint64_t ShiftAmt,
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SelectionDAG &DAG) {
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EVT ElementType = VT.getVectorElementType();
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// Check for ShiftAmt >= element width
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if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
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if (ShiftAmt >= ElementType.getSizeInBits()) {
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if (Opc == X86ISD::VSRAI)
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ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
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ShiftAmt = ElementType.getSizeInBits() - 1;
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else
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return DAG.getConstant(0, VT);
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}
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@ -11115,6 +11116,56 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
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assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
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&& "Unknown target vector shift-by-constant node");
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// Fold this packed vector shift into a build vector if SrcOp is a
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// vector of ConstantSDNodes or UNDEFs.
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if (ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
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SmallVector<SDValue, 8> Elts;
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unsigned NumElts = SrcOp->getNumOperands();
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ConstantSDNode *ND;
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switch(Opc) {
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default: llvm_unreachable(0);
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case X86ISD::VSHLI:
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for (unsigned i=0; i!=NumElts; ++i) {
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SDValue CurrentOp = SrcOp->getOperand(i);
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if (CurrentOp->getOpcode() == ISD::UNDEF) {
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Elts.push_back(CurrentOp);
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continue;
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}
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ND = cast<ConstantSDNode>(CurrentOp);
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const APInt &C = ND->getAPIntValue();
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Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
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}
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break;
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case X86ISD::VSRLI:
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for (unsigned i=0; i!=NumElts; ++i) {
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SDValue CurrentOp = SrcOp->getOperand(i);
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if (CurrentOp->getOpcode() == ISD::UNDEF) {
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Elts.push_back(CurrentOp);
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continue;
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}
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ND = cast<ConstantSDNode>(CurrentOp);
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const APInt &C = ND->getAPIntValue();
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Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
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}
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break;
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case X86ISD::VSRAI:
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for (unsigned i=0; i!=NumElts; ++i) {
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SDValue CurrentOp = SrcOp->getOperand(i);
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if (CurrentOp->getOpcode() == ISD::UNDEF) {
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Elts.push_back(CurrentOp);
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continue;
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}
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ND = cast<ConstantSDNode>(CurrentOp);
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const APInt &C = ND->getAPIntValue();
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Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
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}
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break;
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}
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
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}
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return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
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}
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160
test/CodeGen/X86/vec_shift5.ll
Normal file
160
test/CodeGen/X86/vec_shift5.ll
Normal file
@ -0,0 +1,160 @@
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; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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; Verify that we correctly fold target specific packed vector shifts by
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; immediate count into a simple build_vector when the elements of the vector
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; in input to the packed shift are all constants or undef.
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define <8 x i16> @test1() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> <i16 1, i16 2, i16 4, i16 8, i16 1, i16 2, i16 4, i16 8>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test2() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test3() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i16 8, i16 16, i16 32>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test4() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 1, i32 2, i32 4, i32 8>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test5() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test6() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test7() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 1, i64 2>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test8() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test9() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test10() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test11() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test12() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: psra
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test13() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <8 x i16> @test14() {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 15, i16 8, i16 undef, i16 undef, i16 31, i16 undef, i16 64, i16 128>, i32 3)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: psrl
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @test15() {
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%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 undef, i32 8, i32 undef, i32 32>, i32 3)
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test15
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <2 x i64> @test16() {
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%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 undef, i64 31>, i32 3)
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test16
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; CHECK-NOT: psll
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; CHECK: movaps
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; CHECK-NEXT: ret
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
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declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
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declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
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declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
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declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
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declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32)
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