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GlobalISel: Implement known bits for G_MERGE_VALUES
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@ -241,6 +241,12 @@ public:
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static KnownBits computeForAddSub(bool Add, bool NSW, const KnownBits &LHS,
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KnownBits RHS);
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/// Insert the bits from a smaller known bits starting at bitPosition.
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void insertBits(const KnownBits &SubBits, unsigned BitPosition) {
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Zero.insertBits(SubBits.Zero, BitPosition);
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One.insertBits(SubBits.One, BitPosition);
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}
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/// Update known bits based on ANDing with RHS.
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KnownBits &operator&=(const KnownBits &RHS);
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@ -387,6 +387,18 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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Known.Zero.setBitsFrom(SrcBitWidth);
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break;
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}
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case TargetOpcode::G_MERGE_VALUES: {
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Register NumOps = MI.getNumOperands();
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unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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for (unsigned I = 0; I != NumOps - 1; ++I) {
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KnownBits SrcOpKnown;
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computeKnownBitsImpl(MI.getOperand(I + 1).getReg(), SrcOpKnown,
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DemandedElts, Depth + 1);
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Known.insertBits(SrcOpKnown, I * OpSize);
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}
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break;
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}
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}
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assert(!Known.hasConflict() && "Bits known to be one AND zero?");
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@ -555,3 +555,26 @@ TEST_F(AArch64GISelMITest, TestKnownBitsExt) {
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EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
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EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
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}
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TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {
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StringRef MIRString = R"(
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%val0:_(s16) = G_CONSTANT i16 35224
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%val1:_(s16) = G_CONSTANT i16 17494
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%val2:_(s16) = G_CONSTANT i16 4659
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%val3:_(s16) = G_CONSTANT i16 43981
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%merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val3
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%mergecopy:_(s64) = COPY %merge
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)";
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setUp(MIRString);
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if (!TM)
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return;
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const uint64_t TestVal = UINT64_C(0xabcd123344568998);
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Register CopyMerge = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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KnownBits Res = Info.getKnownBits(CopyMerge);
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EXPECT_EQ(64u, Res.getBitWidth());
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EXPECT_EQ(TestVal, Res.One.getZExtValue());
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EXPECT_EQ(~TestVal, Res.Zero.getZExtValue());
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}
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