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Fixing bug in rL258132: [X86] Adding support for missing variations of X86 string related instructions

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There was a bug in my rL258132 because there's an overloading of the "movsd" and "cmpsd" instructions, e.g. movsd can be either "Move Data from String to String" (the case I wanted to handle) or "Move or Merge Scalar Double-Precision Floating-Point Value" (the case that causes the asserts).
Added  code for escaping the unfamiliar scenarios and falling back to old behviour.
Also changed the asserts to llvm_unreachable. 

llvm-svn: 258312
This commit is contained in:
Marina Yatsina 2016-01-20 14:03:47 +00:00
parent d1195ef11e
commit b35ff9ba57
1 changed files with 6 additions and 2 deletions
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8
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -1007,7 +1007,7 @@ std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
bool X86AsmParser::IsSIReg(unsigned Reg) {
switch (Reg) {
default:
assert("Only (R|E)SI and (R|E)DI are expected!");
llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
return false;
case X86::RSI:
case X86::ESI:
@ -1024,7 +1024,7 @@ unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
bool IsSIReg) {
switch (RegClassID) {
default:
assert("Unexpected register class");
llvm_unreachable("Unexpected register class");
return Reg;
case X86::GR64RegClassID:
return IsSIReg ? X86::RSI : X86::RDI;
@ -1090,6 +1090,10 @@ bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
RegClassID = X86::GR32RegClassID;
else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
RegClassID = X86::GR16RegClassID;
else
// Unexpexted register class type
// Return false and let a normal complaint about bogus operands happen
return false;
bool IsSI = IsSIReg(FinalReg);
FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);