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[X86] Disable a DAG combine to allow packed AVX512DQ instructions to be consistently used for i64->float/double conversions.
Summary: We already get this right if the i64 didn't come from a load. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47439 llvm-svn: 333393
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@ -37729,6 +37729,11 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
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if (VT == MVT::f16 || VT == MVT::f128)
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return SDValue();
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// If we have AVX512DQ we can use packed conversion instructions unless
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// the VT is f80.
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if (Subtarget.hasDQI() && VT != MVT::f80)
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return SDValue();
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if (!Ld->isVolatile() && !VT.isVector() &&
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ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
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!Subtarget.is64Bit() && LdVT == MVT::i64) {
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@ -410,20 +410,42 @@ define float @u64_to_f(i64 %a) nounwind {
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}
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define float @s64_to_f(i64 %a) nounwind {
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; AVX512_32-LABEL: s64_to_f:
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; AVX512_32: # %bb.0:
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; AVX512_32-NEXT: pushl %eax
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; AVX512_32-NEXT: fildll {{[0-9]+}}(%esp)
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; AVX512_32-NEXT: fstps (%esp)
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; AVX512_32-NEXT: flds (%esp)
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; AVX512_32-NEXT: popl %eax
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; AVX512_32-NEXT: retl
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; AVX512DQVL_32-LABEL: s64_to_f:
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; AVX512DQVL_32: # %bb.0:
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; AVX512DQVL_32-NEXT: pushl %eax
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; AVX512DQVL_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX512DQVL_32-NEXT: vcvtqq2ps %ymm0, %xmm0
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; AVX512DQVL_32-NEXT: vmovss %xmm0, (%esp)
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; AVX512DQVL_32-NEXT: flds (%esp)
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; AVX512DQVL_32-NEXT: popl %eax
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; AVX512DQVL_32-NEXT: vzeroupper
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; AVX512DQVL_32-NEXT: retl
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;
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; AVX512_64-LABEL: s64_to_f:
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; AVX512_64: # %bb.0:
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; AVX512_64-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0
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; AVX512_64-NEXT: retq
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;
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; AVX512DQ_32-LABEL: s64_to_f:
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; AVX512DQ_32: # %bb.0:
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; AVX512DQ_32-NEXT: pushl %eax
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; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX512DQ_32-NEXT: vcvtqq2ps %zmm0, %ymm0
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; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
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; AVX512DQ_32-NEXT: flds (%esp)
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; AVX512DQ_32-NEXT: popl %eax
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; AVX512DQ_32-NEXT: vzeroupper
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; AVX512DQ_32-NEXT: retl
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;
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; AVX512F_32-LABEL: s64_to_f:
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; AVX512F_32: # %bb.0:
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; AVX512F_32-NEXT: pushl %eax
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; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
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; AVX512F_32-NEXT: fstps (%esp)
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; AVX512F_32-NEXT: flds (%esp)
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; AVX512F_32-NEXT: popl %eax
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; AVX512F_32-NEXT: retl
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;
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; SSE2_32-LABEL: s64_to_f:
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; SSE2_32: # %bb.0:
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; SSE2_32-NEXT: pushl %eax
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@ -656,24 +678,54 @@ define double @u64_to_d(i64 %a) nounwind {
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}
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define double @s64_to_d(i64 %a) nounwind {
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; AVX512_32-LABEL: s64_to_d:
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; AVX512_32: # %bb.0:
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; AVX512_32-NEXT: pushl %ebp
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; AVX512_32-NEXT: movl %esp, %ebp
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; AVX512_32-NEXT: andl $-8, %esp
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; AVX512_32-NEXT: subl $8, %esp
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; AVX512_32-NEXT: fildll 8(%ebp)
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; AVX512_32-NEXT: fstpl (%esp)
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; AVX512_32-NEXT: fldl (%esp)
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; AVX512_32-NEXT: movl %ebp, %esp
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; AVX512_32-NEXT: popl %ebp
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; AVX512_32-NEXT: retl
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; AVX512DQVL_32-LABEL: s64_to_d:
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; AVX512DQVL_32: # %bb.0:
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; AVX512DQVL_32-NEXT: pushl %ebp
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; AVX512DQVL_32-NEXT: movl %esp, %ebp
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; AVX512DQVL_32-NEXT: andl $-8, %esp
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; AVX512DQVL_32-NEXT: subl $8, %esp
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; AVX512DQVL_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX512DQVL_32-NEXT: vcvtqq2pd %ymm0, %ymm0
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; AVX512DQVL_32-NEXT: vmovlps %xmm0, (%esp)
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; AVX512DQVL_32-NEXT: fldl (%esp)
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; AVX512DQVL_32-NEXT: movl %ebp, %esp
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; AVX512DQVL_32-NEXT: popl %ebp
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; AVX512DQVL_32-NEXT: vzeroupper
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; AVX512DQVL_32-NEXT: retl
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;
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; AVX512_64-LABEL: s64_to_d:
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; AVX512_64: # %bb.0:
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; AVX512_64-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0
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; AVX512_64-NEXT: retq
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;
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; AVX512DQ_32-LABEL: s64_to_d:
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; AVX512DQ_32: # %bb.0:
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; AVX512DQ_32-NEXT: pushl %ebp
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; AVX512DQ_32-NEXT: movl %esp, %ebp
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; AVX512DQ_32-NEXT: andl $-8, %esp
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; AVX512DQ_32-NEXT: subl $8, %esp
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; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX512DQ_32-NEXT: vcvtqq2pd %zmm0, %zmm0
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; AVX512DQ_32-NEXT: vmovlps %xmm0, (%esp)
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; AVX512DQ_32-NEXT: fldl (%esp)
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; AVX512DQ_32-NEXT: movl %ebp, %esp
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; AVX512DQ_32-NEXT: popl %ebp
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; AVX512DQ_32-NEXT: vzeroupper
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; AVX512DQ_32-NEXT: retl
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;
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; AVX512F_32-LABEL: s64_to_d:
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; AVX512F_32: # %bb.0:
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; AVX512F_32-NEXT: pushl %ebp
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; AVX512F_32-NEXT: movl %esp, %ebp
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; AVX512F_32-NEXT: andl $-8, %esp
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; AVX512F_32-NEXT: subl $8, %esp
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; AVX512F_32-NEXT: fildll 8(%ebp)
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; AVX512F_32-NEXT: fstpl (%esp)
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; AVX512F_32-NEXT: fldl (%esp)
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; AVX512F_32-NEXT: movl %ebp, %esp
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; AVX512F_32-NEXT: popl %ebp
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; AVX512F_32-NEXT: retl
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;
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; SSE2_32-LABEL: s64_to_d:
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; SSE2_32: # %bb.0:
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; SSE2_32-NEXT: pushl %ebp
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