RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

Value initialize MCRegisterClasses. Not sure how could miss this during the MCTargetDesc refactor.

Browse Source 
llvm-svn: 150076
This commit is contained in:
Benjamin Kramer 2012-02-08 14:43:53 +00:00
parent 230a53240a
commit b42d2a7238
2 changed files with 3 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
include/llvm/MC/MCRegisterInfo.h
View File

@ -27,7 +27,7 @@ class MCRegisterClass {
public:
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
private:
unsigned ID;
const char *Name;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
@ -36,17 +36,6 @@ private:
const iterator RegsBegin, RegsEnd;
const unsigned char *const RegSet;
const unsigned RegSetSize;
public:
MCRegisterClass(unsigned id, const char *name,
unsigned RS, unsigned Al, int CC, bool Allocable,
iterator RB, iterator RE, const unsigned char *Bits,
unsigned NumBytes)
: ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
RegSetSize(NumBytes) {
for (iterator i = RegsBegin; i != RegsEnd; ++i)
assert(contains(*i) && "Bit field corrupted.");
}
/// getID() - Return the register class ID number.
///

4
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -367,7 +367,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
OS << " { " << RC.getQualifiedName() + "RegClassID" << ", "
<< '\"' << RC.getName() << "\", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", "
@ -376,7 +376,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
<< RC.getName() << ", " << RC.getName() << " + "
<< RC.getOrder().size() << ", "
<< RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
<< "),\n";
<< " },\n";
}
OS << "};\n\n";