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Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty

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Summary:
Check that any function that has the property set is free of virtual
register operands.

Also, it is actually VirtRegMap (and not the register allocators) that
acutally remove the VReg operands (except for RegAllocFast).

Reviewers: qcolombet

Subscribers: MatzeB, llvm-commits, qcolombet

Differential Revision: http://reviews.llvm.org/D18535

llvm-svn: 264755
This commit is contained in:
Derek Schuff 2016-03-29 17:40:22 +00:00
parent 620c905661
commit b44b894dbb
5 changed files with 20 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/CodeGen/MachineVerifier.cpp
View File

@ -251,6 +251,7 @@ namespace {
void verifyStackFrame();
void verifySlotIndexes() const;
void verifyProperties(const MachineFunction &MF);
};
struct MachineVerifierPass : public MachineFunctionPass {
@ -307,6 +308,19 @@ void MachineVerifier::verifySlotIndexes() const {
}
}
void MachineVerifier::verifyProperties(const MachineFunction &MF) {
// If a pass has introduced virtual registers without clearing the
// AllVRegsAllocated property (or set it without allocating the vregs)
// then report an error.
if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::AllVRegsAllocated) &&
MRI->getNumVirtRegs()) {
report(
"Function has AllVRegsAllocated property but there are VReg operands",
&MF);
}
}
unsigned MachineVerifier::verify(MachineFunction &MF) {
foundErrors = 0;
@ -331,6 +345,8 @@ unsigned MachineVerifier::verify(MachineFunction &MF) {
verifySlotIndexes();
verifyProperties(MF);
visitMachineFunctionBefore();
for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
MFI!=MFE; ++MFI) {

5
lib/CodeGen/RegAllocBasic.cpp
View File

@ -83,11 +83,6 @@ public:
/// RABasic analysis usage.
void getAnalysisUsage(AnalysisUsage &AU) const override;
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated);
}
void releaseMemory() override;
Spiller &spiller() override { return *SpillerInstance; }

4
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -322,10 +322,6 @@ public:
/// RAGreedy analysis usage.
void getAnalysisUsage(AnalysisUsage &AU) const override;
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated);
}
void releaseMemory() override;
Spiller &spiller() override { return *SpillerInstance; }
void enqueue(LiveInterval *LI) override;

5
lib/CodeGen/RegAllocPBQP.cpp
View File

@ -106,11 +106,6 @@ public:
/// PBQP analysis usage.
void getAnalysisUsage(AnalysisUsage &au) const override;
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated);
}
/// Perform register allocation
bool runOnMachineFunction(MachineFunction &MF) override;

5
lib/CodeGen/VirtRegMap.cpp
View File

@ -176,6 +176,10 @@ public:
void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override;
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::AllVRegsAllocated);
}
};
} // end anonymous namespace
@ -445,4 +449,3 @@ void VirtRegRewriter::rewrite() {
}
}
}