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llvm-svn: 1498
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@ -15,7 +15,6 @@
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// Integer Register Class
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//-----------------------------------------------------------------------------
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// Int register names in same order as enum in class SparcIntRegOrder
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static string const IntRegNames[] =
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@ -38,7 +37,7 @@ class SparcIntRegOrder{
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// --- following colors are volatile across function calls
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// %g0 can't be used for coloring - always 0
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//%g1-%g5 (g6-7 are reserved for system)
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o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
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// %o6 is sp,
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@ -59,9 +58,12 @@ class SparcIntRegOrder{
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i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6
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//*** NOTE: If we decide to use globals, some of them are volatile
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//**** see sparc64ABI (change isRegVloatile method below)
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//*** NOTE: If we decide to use some %g regs, they are volatile
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// (see sparc64ABI)
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// Move the %g regs from the end of the enumeration to just above the
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// enumeration of %o0 (change StartOfAllRegs below)
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// change isRegVloatile method below
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// Also change IntRegNames above.
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};
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@ -110,6 +112,9 @@ class SparcIntRegClass : public MachineRegClassInfo
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};
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//-----------------------------------------------------------------------------
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// Float Register Class
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//-----------------------------------------------------------------------------
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@ -158,7 +163,6 @@ class SparcFloatRegOrder{
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}
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};
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@ -219,10 +223,6 @@ class SparcIntCCRegOrder{
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return IntCCRegNames[reg];
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}
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// according to Sparc 64 ABI, %ccr is volatile
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inline bool isRegVolatile(const int Reg) const { return true; }
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};
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@ -238,13 +238,15 @@ public:
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Node->setColor(0); // only one int cc reg is available
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}
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// according to Sparc 64 ABI, %ccr is volatile
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//
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inline bool isRegVolatile(const int Reg) const { return true; }
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};
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//-----------------------------------------------------------------------------
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// Float CC Register Class
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// Only 4 Float CC registers are available
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@ -271,10 +273,6 @@ class SparcFloatCCRegOrder{
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return FloatCCRegNames[reg];
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}
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// according to Sparc 64 ABI, all %fp regs are volatile
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inline bool isRegVolatile(const int Reg) const { return true; }
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};
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@ -293,7 +291,9 @@ public:
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Node->setColor(c);
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}
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// *** TODO: Check this
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// according to Sparc 64 ABI, all %fp CC regs are volatile
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//
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inline bool isRegVolatile(const int Reg) const { return true; }
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@ -1161,31 +1161,28 @@ MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
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//----------------------------------------------------------------------------
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// This method inserts caller saving/restoring instructons before/after
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// a call machine instruction.
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// a call machine instruction. The caller saving/restoring instructions are
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// inserted like:
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//
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// ** caller saving instructions
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// other instructions inserted for the call by ColorCallArg
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// CALL instruction
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// other instructions inserted for the call ColorCallArg
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// ** caller restoring instructions
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//
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//----------------------------------------------------------------------------
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void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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const BasicBlock *BB,
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PhyRegAlloc &PRA) const {
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// assert( (getInstrInfo()).isCall( MInst->getOpCode() ) );
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// Clear the temp area of the stack
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//PRA.mcInfo.popAllTempValues(target);
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// TODO*** Don't do this since we can have a situation like
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/*
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stx %o1 %i6 1999 <--- inserted by this code
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stx %o5 %i6 2007
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*****
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stx %o1 %i6 2007 ???? <-- inserted by statck2stack call arg
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*/
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// has set to record which registers were saved/restored
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//
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hash_set<unsigned> PushedRegSet;
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// Now find the LR of the return value of the call
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// The last *implicit operand* is the return value of a call
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// Insert it to to he PushedRegSet since we must not save that register
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@ -1350,11 +1347,6 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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} // for each value in the LV set after instruction
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// Clear the temp area of the stack
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// PRA.mcInfo.popAllTempValues(target);
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// TODO *** see above call - optimize later
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}
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//---------------------------------------------------------------------------
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