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[ARM][MVE] Add complex vector intrinsics

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Summary:
This patch adds intrinsics for the following MVE instructions:
* VCADD, VHCADD
* VCMUL
* VCMLA

Each of the above 3 groups has a corresponding new LLVM IR intrinsic.

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: MarkMurrayARM

Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D71190
This commit is contained in:
Mikhail Maltsev 2019-12-09 12:05:59 +00:00
parent 1d7bf55fa9
commit b45bad1e62
5 changed files with 1612 additions and 0 deletions
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36
include/llvm/IR/IntrinsicsARM.td
View File

@ -921,6 +921,42 @@ def int_arm_mve_vrmulh: Intrinsic<
[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
// Intrinsic with a predicated and a non-predicated case. The predicated case
// has two additional parameters: inactive (the value for inactive lanes, can
// be undef) and predicate.
multiclass MVEMXPredicated<list<LLVMType> rets, list<LLVMType> flags,
list<LLVMType> params, LLVMType inactive,
LLVMType predicate,
list<IntrinsicProperty> props = []> {
def "": Intrinsic<rets, flags # params, props>;
def _predicated: Intrinsic<rets, flags # [inactive] # params # [predicate],
props>;
}
// The first two parameters are compile-time constants:
// * Halving: is the a halving (vhcaddq) or non-halving (vcaddq) instruction
// * Rotation angle: 0 mean 90 deg, 1 means 180 deg
defm int_arm_mve_vcaddq : MVEMXPredicated<
[llvm_anyvector_ty],
[llvm_i32_ty, llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
LLVMMatchType<0>, llvm_anyvector_ty, [IntrNoMem]>;
// The first operand of the following two intrinsics is the rotation angle
// (must be a compile-time constant):
// 0 - 0 deg
// 1 - 90 deg
// 2 - 180 deg
// 3 - 270 deg
defm int_arm_mve_vcmulq : MVEMXPredicated<
[llvm_anyvector_ty],
[llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
LLVMMatchType<0>, llvm_anyvector_ty, [IntrNoMem]>;
defm int_arm_mve_vcmlaq : MVEPredicated<
[llvm_anyvector_ty],
[llvm_i32_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
llvm_anyvector_ty, [IntrNoMem]>;
def int_arm_mve_vld2q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty], [IntrReadMem]>;
def int_arm_mve_vld4q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [llvm_anyptr_ty], [IntrReadMem]>;

178
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -233,6 +233,22 @@ private:
void SelectMVE_VADCSBC(SDNode *N, uint16_t OpcodeWithCarry,
uint16_t OpcodeWithNoCarry, bool Add, bool Predicated);
/// Select MVE complex vector addition intrinsic
/// OpcodesInt are opcodes for non-halving addition of complex integer vectors
/// OpcodesHInt are opcodes for halving addition of complex integer vectors
/// OpcodesFP are opcodes for addition of complex floating point vectors
void SelectMVE_VCADD(SDNode *N, const uint16_t *OpcodesInt,
const uint16_t *OpcodesHInt, const uint16_t *OpcodesFP,
bool Predicated);
/// Select MVE complex vector multiplication intrinsic
void SelectMVE_VCMUL(SDNode *N, uint16_t OpcodeF16, uint16_t OpcodeF32,
bool Predicated);
/// Sekect NVE complex vector multiply-add intrinsic
void SelectMVE_VCMLA(SDNode *N, uint16_t OpcodeF16, uint16_t OpcodeF32,
bool Predicated);
/// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
/// should be 2 or 4. The opcode array specifies the instructions
/// used for 8, 16 and 32-bit lane sizes respectively, and each
@ -2517,6 +2533,138 @@ void ARMDAGToDAGISel::SelectMVE_VADCSBC(SDNode *N, uint16_t OpcodeWithCarry,
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
}
/// Convert an SDValue to a boolean value. SDVal must be a compile-time constant
static bool SDValueToConstBool(SDValue SDVal) {
ConstantSDNode *SDValConstant = dyn_cast<ConstantSDNode>(SDVal);
assert(SDValConstant && "expected a compile-time constant");
uint64_t Value = SDValConstant->getZExtValue();
assert((Value == 0 || Value == 1) && "expected value 0 or 1");
return Value;
}
/// Select an opcode based on a floating point vector type. One opcode
/// corresponds to 16-bit floating point element type, the other to two 32-bit
/// element type.
/// Other types are not allowed
static uint16_t SelectFPOpcode(EVT VT, uint16_t OpcodeF16, uint16_t OpcodeF32) {
assert(VT.isFloatingPoint() && VT.isVector() &&
"expected a floating-point vector");
switch (VT.getVectorElementType().getSizeInBits()) {
case 16:
return OpcodeF16;
case 32:
return OpcodeF32;
default:
llvm_unreachable("bad vector element size");
}
}
void ARMDAGToDAGISel::SelectMVE_VCADD(SDNode *N, const uint16_t *OpcodesInt,
const uint16_t *OpcodesHInt,
const uint16_t *OpcodesFP,
bool Predicated) {
EVT VT = N->getValueType(0);
SDLoc Loc(N);
bool IsHalved = SDValueToConstBool(N->getOperand(1));
bool IsAngle270 = SDValueToConstBool(N->getOperand(2));
bool IsFP = VT.isFloatingPoint();
if (IsHalved)
assert(!IsFP && "vhcaddq requires integer vector type");
uint16_t Opcode;
if (IsFP) {
Opcode = SelectFPOpcode(VT, OpcodesFP[0], OpcodesFP[1]);
} else {
const uint16_t *Opcodes = IsHalved ? OpcodesHInt : OpcodesInt;
switch (VT.getVectorElementType().getSizeInBits()) {
case 8:
Opcode = Opcodes[0];
break;
case 16:
Opcode = Opcodes[1];
break;
case 32:
Opcode = Opcodes[2];
break;
default:
llvm_unreachable("bad vector element size");
}
}
int FirstInputOp = Predicated ? 4 : 3;
SmallVector<SDValue, 8> Ops;
// Vectors
Ops.push_back(N->getOperand(FirstInputOp));
Ops.push_back(N->getOperand(FirstInputOp + 1));
// Rotation
Ops.push_back(CurDAG->getTargetConstant(IsAngle270, Loc, MVT::i32));
if (Predicated)
AddMVEPredicateToOps(Ops, Loc,
N->getOperand(FirstInputOp + 2), // predicate
N->getOperand(FirstInputOp - 1)); // inactive
else
AddEmptyMVEPredicateToOps(Ops, Loc, VT);
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
}
static uint32_t GetCMulRotation(SDValue V) {
const ConstantSDNode *RotConstant = dyn_cast<ConstantSDNode>(V);
assert(RotConstant && "expected a compile-time constant");
uint64_t RotValue = RotConstant->getZExtValue();
assert(RotValue < 4 && "expected value in range [0, 3]");
return RotValue;
}
void ARMDAGToDAGISel::SelectMVE_VCMUL(SDNode *N, uint16_t OpcodeF16,
uint16_t OpcodeF32, bool Predicated) {
EVT VT = N->getValueType(0);
SDLoc Loc(N);
int FirstInputOp = Predicated ? 3 : 2;
SmallVector<SDValue, 8> Ops;
// Vectors
Ops.push_back(N->getOperand(FirstInputOp));
Ops.push_back(N->getOperand(FirstInputOp + 1));
// Rotation
uint32_t RotValue = GetCMulRotation(N->getOperand(1));
Ops.push_back(CurDAG->getTargetConstant(RotValue, Loc, MVT::i32));
if (Predicated)
AddMVEPredicateToOps(Ops, Loc,
N->getOperand(FirstInputOp + 2), // predicate
N->getOperand(FirstInputOp - 1)); // inactive
else
AddEmptyMVEPredicateToOps(Ops, Loc, VT);
uint16_t Opcode = SelectFPOpcode(VT, OpcodeF16, OpcodeF32);
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
}
void ARMDAGToDAGISel::SelectMVE_VCMLA(SDNode *N, uint16_t OpcodeF16,
uint16_t OpcodeF32, bool Predicated) {
SDLoc Loc(N);
SmallVector<SDValue, 8> Ops;
// The 3 vector operands
for (int i = 2; i < 5; ++i)
Ops.push_back(N->getOperand(i));
// Rotation
uint32_t RotValue = GetCMulRotation(N->getOperand(1));
Ops.push_back(CurDAG->getTargetConstant(RotValue, Loc, MVT::i32));
if (Predicated)
AddMVEPredicateToOps(Ops, Loc, N->getOperand(5));
else
AddEmptyMVEPredicateToOps(Ops, Loc);
EVT VT = N->getValueType(0);
uint16_t Opcode = SelectFPOpcode(VT, OpcodeF16, OpcodeF32);
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), makeArrayRef(Ops));
}
void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,
const uint16_t *const *Opcodes) {
EVT VT = N->getValueType(0);
@ -4361,6 +4509,36 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
SelectMVE_VADCSBC(N, ARM::MVE_VADC, ARM::MVE_VADCI, true,
IntNo == Intrinsic::arm_mve_vadc_predicated);
return;
case Intrinsic::arm_mve_vcaddq:
case Intrinsic::arm_mve_vcaddq_predicated: {
static const uint16_t OpcodesInt[] = {
ARM::MVE_VCADDi8, ARM::MVE_VCADDi16, ARM::MVE_VCADDi32,
};
static const uint16_t OpcodesHInt[] = {
ARM::MVE_VHCADDs8, ARM::MVE_VHCADDs16, ARM::MVE_VHCADDs32,
};
static const uint16_t OpcodesFP[] = {
ARM::MVE_VCADDf16, ARM::MVE_VCADDf32,
};
SelectMVE_VCADD(N, OpcodesInt, OpcodesHInt,
OpcodesFP, IntNo == Intrinsic::arm_mve_vcaddq_predicated);
return;
}
case Intrinsic::arm_mve_vcmulq:
case Intrinsic::arm_mve_vcmulq_predicated:
SelectMVE_VCMUL(N, ARM::MVE_VCMULf16, ARM::MVE_VCMULf32,
IntNo == Intrinsic::arm_mve_vcmulq_predicated);
return;
case Intrinsic::arm_mve_vcmlaq:
case Intrinsic::arm_mve_vcmlaq_predicated:
SelectMVE_VCMLA(N, ARM::MVE_VCMLAf16, ARM::MVE_VCMLAf32,
IntNo == Intrinsic::arm_mve_vcmlaq_predicated);
return;
}
break;
}

870
test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll Normal file
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@ -0,0 +1,870 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>)
declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>)
declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>)
declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>)
declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>)
declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>)
declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>)
declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>)
declare <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32, i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>)
declare <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32, i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>)
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vcaddq_rot90_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vcaddq_rot90_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vcaddq_rot90_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vcaddq_rot90_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vcaddq_rot90_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vcaddq_rot90_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vcaddq_rot90_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.f16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 0, i32 0, <8 x half> %a, <8 x half> %b)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcaddq_rot90_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.f32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 0, i32 0, <4 x float> %a, <4 x float> %b)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vcaddq_rot270_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vcaddq_rot270_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vcaddq_rot270_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vcaddq_rot270_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i8 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vcaddq_rot270_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vcaddq_rot270_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.i32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vcaddq_rot270_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.f16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 0, i32 1, <8 x half> %a, <8 x half> %b)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcaddq_rot270_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcadd.f32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 0, i32 1, <4 x float> %a, <4 x float> %b)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 0, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 0, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 1, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 1, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 0, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot90_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 0, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i8 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.i32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 0, i32 1, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcaddq_rot270_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcaddt.f32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 0, i32 1, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vhcaddq_rot90_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vhcadd.s8 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vhcaddq_rot90_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vhcadd.s16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vhcaddq_rot90_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vhcadd.s32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_vhcaddq_rot270_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vhcadd.s8 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_vhcaddq_rot270_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vhcadd.s16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %a, <8 x i16> %b)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test_vhcaddq_rot270_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vhcadd.s32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_x_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s8 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_x_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot270_x_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s8 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot270_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot270_x_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_m_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s8 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_m_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_m_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot270_m_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s8 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, <16 x i1> %1)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot270_m_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, <8 x i1> %1)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot270_m_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhcaddt.s32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, <4 x i1> %1)
ret <4 x i32> %2
}

205
test/CodeGen/Thumb2/mve-intrinsics/vcmlaq.ll Normal file
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@ -0,0 +1,205 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>)
declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>)
declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>)
declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>)
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
; CHECK-LABEL: test_vcmlaq_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f16 q0, q1, q2, #0
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %a, <8 x half> %b, <8 x half> %c)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_vcmlaq_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f32 q0, q1, q2, #0
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
; CHECK-LABEL: test_vcmlaq_rot90_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %a, <8 x half> %b, <8 x half> %c)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_vcmlaq_rot90_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
; CHECK-LABEL: test_vcmlaq_rot180_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f16 q0, q1, q2, #180
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %a, <8 x half> %b, <8 x half> %c)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_vcmlaq_rot180_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f32 q0, q1, q2, #180
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
; CHECK-LABEL: test_vcmlaq_rot270_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %a, <8 x half> %b, <8 x half> %c)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_vcmlaq_rot270_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmla.f32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #0
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #0
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_rot90_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_rot90_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 1, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_rot180_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #180
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 2, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_rot180_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #180
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 2, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_rot270_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 3, <8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_m_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, i16 zeroext %p) {
; CHECK-LABEL: test_vcmlaq_rot270_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmlat.f32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 3, <4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %1)
ret <4 x float> %2
}

323
test/CodeGen/Thumb2/mve-intrinsics/vcmulq.ll Normal file
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@ -0,0 +1,323 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>)
declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>)
declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>)
declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>)
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vcmulq_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f16 q0, q0, q1, #0
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %a, <8 x half> %b)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcmulq_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f32 q2, q0, q1, #0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %a, <4 x float> %b)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vcmulq_rot90_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %a, <8 x half> %b)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcmulq_rot90_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %a, <4 x float> %b)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vcmulq_rot180_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f16 q0, q0, q1, #180
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %a, <8 x half> %b)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcmulq_rot180_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f32 q2, q0, q1, #180
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %a, <4 x float> %b)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vcmulq_rot270_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %a, <8 x half> %b)
ret <8 x half> %0
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_vcmulq_rot270_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmul.f32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %a, <4 x float> %b)
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q1, q2, #0
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q0, q1, q2, #0
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot90_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot90_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q0, q1, q2, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot180_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q1, q2, #180
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot180_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q0, q1, q2, #180
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot270_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> %inactive, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot270_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q0, q1, q2, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> %inactive, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q0, q1, #0
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q2, q0, q1, #0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot90_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q0, q1, #90
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot90_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q2, q0, q1, #90
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot180_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q0, q1, #180
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot180_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q2, q0, q1, #180
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}
define arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot270_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f16 q0, q0, q1, #270
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> undef, <8 x half> %a, <8 x half> %b, <8 x i1> %1)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vcmulq_rot270_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vcmult.f32 q2, q0, q1, #270
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> undef, <4 x float> %a, <4 x float> %b, <4 x i1> %1)
ret <4 x float> %2
}