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Record all of the expanded registers in the DAG and machine instr, fixing
several bugs in inline asm expanded operands. llvm-svn: 26332
This commit is contained in:
Chris Lattner
parent
1ee7e91e5c
commit
b4951fbe82
@ -569,19 +569,26 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
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exit(1);
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}
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char ExtraCode = 0; // FIXME:
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// Okay, we finally have an operand number. Ask the target to print this
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// Okay, we finally have a value number. Ask the target to print this
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// operand!
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if (CurVariant == -1 || CurVariant == AsmPrinterVariant)
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if (CurVariant == -1 || CurVariant == AsmPrinterVariant) {
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unsigned OpNo = 1;
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// Scan to find the machine operand number for the operand.
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for (; Val; --Val)
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OpNo += MI->getOperand(OpNo).getImmedValue()+1;
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++OpNo; // Skip over the ID number.
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if (const_cast<AsmPrinter*>(this)->
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PrintAsmOperand(MI, Val+1, AsmPrinterVariant,
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PrintAsmOperand(MI, OpNo, AsmPrinterVariant,
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Modifier[0] ? Modifier : 0)) {
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std::cerr << "Invalid operand found in inline asm: '"
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<< AsmStr << "'\n";
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MI->dump();
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exit(1);
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}
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}
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break;
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}
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case '{':
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@ -309,23 +309,32 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
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MI->addExternalSymbolOperand(AsmStr, false);
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// Add all of the operand registers to the instruction.
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for (unsigned i = 2; i != NumOps; i += 2) {
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unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue();
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switch (Flags) {
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for (unsigned i = 2; i != NumOps;) {
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unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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unsigned NumOps = Flags >> 3;
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MI->addZeroExtImm64Operand(NumOps);
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++i; // Skip the ID value.
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switch (Flags & 7) {
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default: assert(0 && "Bad flags!");
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case 1: { // Use of register.
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Use);
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case 1: // Use of register.
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for (; NumOps; --NumOps, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Use);
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}
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break;
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}
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case 2: { // Def of register.
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Def);
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case 2: // Def of register.
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for (; NumOps; --NumOps, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Def);
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}
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break;
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}
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case 3: { // Immediate.
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assert(NumOps == 1 && "Unknown immediate value!");
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uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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MI->addZeroExtImm64Operand(Val);
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++i;
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break;
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}
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}
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@ -113,6 +113,18 @@ namespace {
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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SDOperand getCopyFromRegs(SelectionDAG &DAG,
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SDOperand &Chain, SDOperand &Flag);
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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SDOperand &Chain, SDOperand &Flag);
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker and includes the number of
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/// values added into it.
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void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
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std::vector<SDOperand> &Ops);
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};
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}
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@ -1195,7 +1207,41 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
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}
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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SDOperand &Chain, SDOperand &Flag) {
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if (Regs.size() == 1) {
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// If there is a single register and the types differ, this must be
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// a promotion.
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if (RegVT != ValueVT) {
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if (MVT::isInteger(RegVT))
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Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
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else
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Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
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}
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Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
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Flag = Chain.getValue(1);
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} else {
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
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DAG.getConstant(i, MVT::i32));
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Chain = DAG.getCopyToReg(Chain, Regs[i], Part, Flag);
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Flag = Chain.getValue(1);
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}
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}
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}
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker and includes the number of
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/// values added into it.
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void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
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std::vector<SDOperand> &Ops) {
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Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
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for (unsigned i = 0, e = Regs.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(Regs[i], RegVT));
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}
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/// isAllocatableRegister - If the specified register is safe to allocate,
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/// i.e. it isn't a stack pointer or some other special register, return the
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@ -1453,96 +1499,92 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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// Add information to the INLINEASM node to know that this register is
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// set.
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// FIXME:
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// FIXME: Handle multiple regs here.
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// FIXME:
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unsigned DestReg = Regs.Regs[0];
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AsmNodeOperands.push_back(DAG.getRegister(DestReg, Regs.RegVT));
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AsmNodeOperands.push_back(DAG.getConstant(2, MVT::i32)); // ISDEF
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Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
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break;
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}
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case InlineAsm::isInput: {
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Value *CallOperand = I.getOperand(OpNum);
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OpNum++; // Consumes a call operand.
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SDOperand ResOp;
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unsigned ResOpType;
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SDOperand InOperandVal = getValue(CallOperand);
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if (isdigit(ConstraintCode[0])) { // Matching constraint?
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// If this is required to match an output register we have already set,
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// just use its register.
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unsigned OperandNo = atoi(ConstraintCode.c_str());
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unsigned SrcReg;
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SrcReg = cast<RegisterSDNode>(AsmNodeOperands[OperandNo*2+2])->getReg();
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ResOp = DAG.getRegister(SrcReg, ConstraintVTs[i]);
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ResOpType = 1;
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Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
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Flag = Chain.getValue(1);
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// Scan until we find the definition we already emitted of this operand.
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// When we find it, create a RegsForValue operand.
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unsigned CurOp = 2; // The first operand.
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for (; OperandNo; --OperandNo) {
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// Advance to the next operand.
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unsigned NumOps =
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
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assert((NumOps & 7) == 2 /*REGDEF*/ &&
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"Skipped past definitions?");
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CurOp += (NumOps>>3)+1;
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}
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unsigned NumOps =
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
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assert((NumOps & 7) == 2 /*REGDEF*/ &&
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"Skipped past definitions?");
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// Add NumOps>>3 registers to MatchedRegs.
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RegsForValue MatchedRegs;
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MatchedRegs.ValueVT = InOperandVal.getValueType();
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MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
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for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
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unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
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MatchedRegs.Regs.push_back(Reg);
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}
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// Use the produced MatchedRegs object to
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MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
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} else {
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TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
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if (ConstraintCode.size() == 1) // not a physreg name.
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CTy = TLI.getConstraintType(ConstraintCode[0]);
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switch (CTy) {
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default: assert(0 && "Unknown constraint type! FAIL!");
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case TargetLowering::C_RegisterClass: {
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// Copy the input into the appropriate registers.
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RegsForValue InRegs =
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GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
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false, true, OutputRegs, InputRegs);
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// FIXME: should be match fail.
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assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
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if (InRegs.Regs.size() == 1) {
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// If there is a single register and the types differ, this must be
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// a promotion.
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if (InRegs.RegVT != InRegs.ValueVT) {
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if (MVT::isInteger(InRegs.RegVT))
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InOperandVal = DAG.getNode(ISD::ANY_EXTEND, InRegs.RegVT,
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InOperandVal);
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else
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InOperandVal = DAG.getNode(ISD::FP_EXTEND, InRegs.RegVT,
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InOperandVal);
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}
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Chain = DAG.getCopyToReg(Chain, InRegs.Regs[0], InOperandVal, Flag);
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Flag = Chain.getValue(1);
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ResOp = DAG.getRegister(InRegs.Regs[0], InRegs.RegVT);
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} else {
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for (unsigned i = 0, e = InRegs.Regs.size(); i != e; ++i) {
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SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, InRegs.RegVT,
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InOperandVal,
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DAG.getConstant(i, MVT::i32));
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Chain = DAG.getCopyToReg(Chain, InRegs.Regs[i], Part, Flag);
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Flag = Chain.getValue(1);
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}
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ResOp = DAG.getRegister(InRegs.Regs[0], InRegs.RegVT);
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}
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ResOpType = 1;
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break;
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}
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case TargetLowering::C_Other:
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if (CTy == TargetLowering::C_Other) {
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if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
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assert(0 && "MATCH FAIL!");
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ResOp = InOperandVal;
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ResOpType = 3;
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// Add information to the INLINEASM node to know about this input.
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unsigned ResOpType = 3 /*imm*/ | (1 << 3);
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AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
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AsmNodeOperands.push_back(InOperandVal);
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break;
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}
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assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
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// Copy the input into the appropriate registers.
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RegsForValue InRegs =
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GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
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false, true, OutputRegs, InputRegs);
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// FIXME: should be match fail.
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assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
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InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
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InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
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break;
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}
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// Add information to the INLINEASM node to know about this input.
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AsmNodeOperands.push_back(ResOp);
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AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
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break;
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}
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case InlineAsm::isClobber:
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// Nothing to do.
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case InlineAsm::isClobber: {
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RegsForValue ClobberedRegs =
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GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
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OutputRegs, InputRegs);
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// Add the clobbered value to the operand list, so that the register
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// allocator is aware that the physreg got clobbered.
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if (!ClobberedRegs.Regs.empty())
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ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
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break;
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}
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}
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}
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// Finish up input operands.
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