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[DAG] SimplifyMultipleUseDemandedBits - drop unnecessary *_EXTEND_VECTOR_INREG cases

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For little endian targets, if we only need the lowest element and none of the extended bits then we can just use the (bitcasted) source vector directly.

We already do this in SimplifyDemandedBits, this adds the SimplifyMultipleUseDemandedBits equivalent.
This commit is contained in:
Simon Pilgrim 2020-06-22 12:11:11 +01:00
parent aa81d449a8
commit b4c2d312b7
2 changed files with 15 additions and 3 deletions
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15
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -773,6 +773,21 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
return Op0;
break;
}
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG: {
// If we only want the lowest element and none of extended bits, then we can
// return the bitcasted source vector.
SDValue Src = Op.getOperand(0);
EVT SrcVT = Src.getValueType();
EVT DstVT = Op.getValueType();
if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() &&
DAG.getDataLayout().isLittleEndian() &&
DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) {
return DAG.getBitcast(DstVT, Src);
}
break;
}
case ISD::INSERT_VECTOR_ELT: {
// If we don't demand the inserted element, return the base vector.
SDValue Vec = Op.getOperand(0);

3
test/CodeGen/X86/known-signbits-vector.ll
View File

@ -389,7 +389,6 @@ define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4
; X86-NEXT: vmovdqa {{.*#+}} xmm2 = [4,0,8,0]
; X86-NEXT: vpxor %xmm2, %xmm0, %xmm0
; X86-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; X86-NEXT: vpmovsxdq %xmm1, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm2
; X86-NEXT: vpor %xmm1, %xmm2, %xmm1
; X86-NEXT: vpxor %xmm0, %xmm1, %xmm0
@ -407,7 +406,6 @@ define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4
; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [4,8]
; X64-AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; X64-AVX1-NEXT: vpmovsxdq %xmm1, %xmm1
; X64-AVX1-NEXT: vpand %xmm1, %xmm0, %xmm2
; X64-AVX1-NEXT: vpor %xmm1, %xmm2, %xmm1
; X64-AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
@ -420,7 +418,6 @@ define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4
; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [4,8]
; X64-AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; X64-AVX2-NEXT: vpmovsxdq %xmm1, %xmm1
; X64-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm2
; X64-AVX2-NEXT: vpor %xmm1, %xmm2, %xmm1
; X64-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0