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[ARM] bottom-top mul support ARMParallelDSP
Originally committed in rL342210 but was reverted in rL342260 because it was causing issues in vectorized code, because I had forgotten to ensure that we're operating on scalar values. Original commit message: On failing to find sequences that can be converted into dual macs, try to find sequential 16-bit loads that are used by muls which we can then use smultb, smulbt, smultt with a wide load. Differential Revision: https://reviews.llvm.org/D51983 llvm-svn: 342870
This commit is contained in:
Sam Parker
parent
185de7198e
commit
b4d8a969b6
@ -55,6 +55,7 @@ namespace {
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using ReductionList = SmallVector<Reduction, 8>;
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using ValueList = SmallVector<Value*, 8>;
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using MemInstList = SmallVector<Instruction*, 8>;
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using LoadInstList = SmallVector<LoadInst*, 8>;
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using PMACPair = std::pair<BinOpChain*,BinOpChain*>;
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using PMACPairList = SmallVector<PMACPair, 8>;
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using Instructions = SmallVector<Instruction*,16>;
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@ -63,7 +64,8 @@ namespace {
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struct OpChain {
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Instruction *Root;
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ValueList AllValues;
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MemInstList VecLd; // List of all load instructions.
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MemInstList VecLd; // List of all sequential load instructions.
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LoadInstList Loads; // List of all load instructions.
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MemLocList MemLocs; // All memory locations read by this tree.
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bool ReadOnly = true;
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@ -76,8 +78,10 @@ namespace {
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if (auto *I = dyn_cast<Instruction>(V)) {
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if (I->mayWriteToMemory())
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ReadOnly = false;
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if (auto *Ld = dyn_cast<LoadInst>(V))
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if (auto *Ld = dyn_cast<LoadInst>(V)) {
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MemLocs.push_back(MemoryLocation(Ld->getPointerOperand(), Size));
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Loads.push_back(Ld);
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}
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}
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}
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}
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@ -135,6 +139,7 @@ namespace {
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/// exchange the halfwords of the second operand before performing the
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/// arithmetic.
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bool MatchSMLAD(Function &F);
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bool MatchTopBottomMuls(BasicBlock *LoopBody);
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public:
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static char ID;
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@ -203,6 +208,8 @@ namespace {
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LLVM_DEBUG(dbgs() << "\n== Parallel DSP pass ==\n");
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LLVM_DEBUG(dbgs() << " - " << F.getName() << "\n\n");
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Changes = MatchSMLAD(F);
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if (!Changes)
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Changes = MatchTopBottomMuls(Header);
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return Changes;
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}
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};
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@ -496,10 +503,10 @@ static void MatchReductions(Function &F, Loop *TheLoop, BasicBlock *Header,
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);
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}
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static void AddMACCandidate(OpChainList &Candidates,
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static void AddMulCandidate(OpChainList &Candidates,
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Instruction *Mul,
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Value *MulOp0, Value *MulOp1) {
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LLVM_DEBUG(dbgs() << "OK, found acc mul:\t"; Mul->dump());
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LLVM_DEBUG(dbgs() << "OK, found mul:\t"; Mul->dump());
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assert(Mul->getOpcode() == Instruction::Mul &&
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"expected mul instruction");
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ValueList LHS;
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@ -533,14 +540,14 @@ static void MatchParallelMACSequences(Reduction &R,
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break;
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case Instruction::Mul:
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if (match (I, (m_Mul(m_Value(MulOp0), m_Value(MulOp1))))) {
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AddMACCandidate(Candidates, I, MulOp0, MulOp1);
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AddMulCandidate(Candidates, I, MulOp0, MulOp1);
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return false;
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}
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break;
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case Instruction::SExt:
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if (match (I, (m_SExt(m_Mul(m_Value(MulOp0), m_Value(MulOp1)))))) {
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Instruction *Mul = cast<Instruction>(I->getOperand(0));
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AddMACCandidate(Candidates, Mul, MulOp0, MulOp1);
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AddMulCandidate(Candidates, Mul, MulOp0, MulOp1);
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return false;
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}
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break;
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@ -569,23 +576,24 @@ static void AliasCandidates(BasicBlock *Header, Instructions &Reads,
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// the memory locations accessed by the MAC-chains.
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// TODO: we need the read statements when we accept more complicated chains.
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static bool AreAliased(AliasAnalysis *AA, Instructions &Reads,
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Instructions &Writes, OpChainList &MACCandidates) {
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Instructions &Writes, OpChainList &Candidates) {
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LLVM_DEBUG(dbgs() << "Alias checks:\n");
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for (auto &MAC : MACCandidates) {
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LLVM_DEBUG(dbgs() << "mul: "; MAC->Root->dump());
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for (auto &Candidate : Candidates) {
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LLVM_DEBUG(dbgs() << "mul: "; Candidate->Root->dump());
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Candidate->SetMemoryLocations();
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// At the moment, we allow only simple chains that only consist of reads,
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// accumulate their result with an integer add, and thus that don't write
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// memory, and simply bail if they do.
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if (!MAC->ReadOnly)
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if (!Candidate->ReadOnly)
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return true;
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// Now for all writes in the basic block, check that they don't alias with
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// the memory locations accessed by our MAC-chain:
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for (auto *I : Writes) {
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LLVM_DEBUG(dbgs() << "- "; I->dump());
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assert(MAC->MemLocs.size() >= 2 && "expecting at least 2 memlocs");
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for (auto &MemLoc : MAC->MemLocs) {
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assert(Candidate->MemLocs.size() >= 2 && "expecting at least 2 memlocs");
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for (auto &MemLoc : Candidate->MemLocs) {
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if (isModOrRefSet(intersectModRef(AA->getModRefInfo(I, MemLoc),
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ModRefInfo::ModRef))) {
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LLVM_DEBUG(dbgs() << "Yes, aliases found\n");
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@ -599,7 +607,7 @@ static bool AreAliased(AliasAnalysis *AA, Instructions &Reads,
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return false;
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}
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static bool CheckMACMemory(OpChainList &Candidates) {
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static bool CheckMulMemory(OpChainList &Candidates) {
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for (auto &C : Candidates) {
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// A mul has 2 operands, and a narrow op consist of sext and a load; thus
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// we expect at least 4 items in this operand value list.
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@ -607,7 +615,6 @@ static bool CheckMACMemory(OpChainList &Candidates) {
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LLVM_DEBUG(dbgs() << "Operand list too short.\n");
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return false;
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}
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C->SetMemoryLocations();
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ValueList &LHS = static_cast<BinOpChain*>(C.get())->LHS;
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ValueList &RHS = static_cast<BinOpChain*>(C.get())->RHS;
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@ -620,6 +627,133 @@ static bool CheckMACMemory(OpChainList &Candidates) {
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return true;
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}
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static LoadInst *CreateLoadIns(IRBuilder<NoFolder> &IRB, LoadInst *BaseLoad,
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const Type *LoadTy) {
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const unsigned AddrSpace = BaseLoad->getPointerAddressSpace();
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Value *VecPtr = IRB.CreateBitCast(BaseLoad->getPointerOperand(),
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LoadTy->getPointerTo(AddrSpace));
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return IRB.CreateAlignedLoad(VecPtr, BaseLoad->getAlignment());
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}
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/// Attempt to widen loads and use smulbb, smulbt, smultb and smultt muls.
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// TODO: This, like smlad generation, expects the leave operands to be loads
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// that are sign extended. We should be able to handle scalar values as well
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// performing these muls on word x half types to generate smulwb and smulwt.
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bool ARMParallelDSP::MatchTopBottomMuls(BasicBlock *LoopBody) {
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LLVM_DEBUG(dbgs() << "Attempting to find BT|TB muls.\n");
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OpChainList Candidates;
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for (auto &I : *LoopBody) {
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if (I.getOpcode() == Instruction::Mul) {
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Type *Ty = I.getType();
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if (Ty->isIntegerTy() &&
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(Ty->getScalarSizeInBits() == 32 ||
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Ty->getScalarSizeInBits() == 64))
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AddMulCandidate(Candidates, &I, I.getOperand(0), I.getOperand(1));
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}
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}
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if (Candidates.empty())
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return false;
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Instructions Reads;
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Instructions Writes;
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AliasCandidates(LoopBody, Reads, Writes);
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if (AreAliased(AA, Reads, Writes, Candidates))
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return false;
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DenseMap<LoadInst*, Instruction*> LoadUsers;
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DenseMap<LoadInst*, LoadInst*> SeqLoads;
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SmallPtrSet<LoadInst*, 8> OffsetLoads;
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for (unsigned i = 0; i < Candidates.size(); ++i) {
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for (unsigned j = 0; j < Candidates.size(); ++j) {
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if (i == j)
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continue;
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OpChain *MulChain0 = Candidates[i].get();
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OpChain *MulChain1 = Candidates[j].get();
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for (auto *Ld0 : MulChain0->Loads) {
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if (SeqLoads.count(Ld0) || OffsetLoads.count(Ld0))
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continue;
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for (auto *Ld1 : MulChain1->Loads) {
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if (SeqLoads.count(Ld1) || OffsetLoads.count(Ld1))
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continue;
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MemInstList VecMem;
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if (AreSequentialLoads(Ld0, Ld1, VecMem)) {
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SeqLoads[Ld0] = Ld1;
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OffsetLoads.insert(Ld1);
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LoadUsers[Ld0] = MulChain0->Root;
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LoadUsers[Ld1] = MulChain1->Root;
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}
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}
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}
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}
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}
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if (SeqLoads.empty())
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return false;
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IRBuilder<NoFolder> IRB(LoopBody);
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const Type *Ty = IntegerType::get(M->getContext(), 32);
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// We know that at least one of the operands is a SExt of Ld.
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auto GetSExt = [](Instruction *I, LoadInst *Ld, unsigned OpIdx) -> Instruction* {
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if (!isa<Instruction>(I->getOperand(OpIdx)))
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return nullptr;
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Value *SExt = nullptr;
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if (cast<Instruction>(I->getOperand(OpIdx))->getOperand(0) == Ld)
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SExt = I->getOperand(0);
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else
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SExt = I->getOperand(1);
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return cast<Instruction>(SExt);
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};
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LLVM_DEBUG(dbgs() << "Found some sequential loads, now widening:\n");
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for (auto &Pair : SeqLoads) {
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LoadInst *BaseLd = Pair.first;
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LoadInst *OffsetLd = Pair.second;
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IRB.SetInsertPoint(BaseLd);
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LoadInst *WideLd = CreateLoadIns(IRB, BaseLd, Ty);
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LLVM_DEBUG(dbgs() << " - with base load: " << *BaseLd << "\n");
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LLVM_DEBUG(dbgs() << " - created wide load: " << *WideLd << "\n");
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Instruction *BaseUser = LoadUsers[BaseLd];
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Instruction *OffsetUser = LoadUsers[OffsetLd];
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Instruction *BaseSExt = GetSExt(BaseUser, BaseLd, 0);
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if (!BaseSExt)
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BaseSExt = GetSExt(BaseUser, BaseLd, 1);
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Instruction *OffsetSExt = GetSExt(OffsetUser, OffsetLd, 0);
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if (!OffsetSExt)
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OffsetSExt = GetSExt(OffsetUser, OffsetLd, 1);
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assert((BaseSExt && OffsetSExt) && "failed to find SExts");
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// BaseUser needs to: (asr (shl WideLoad, 16), 16)
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// OffsetUser needs to: (asr WideLoad, 16)
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auto *Shl = cast<Instruction>(IRB.CreateShl(WideLd, 16));
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auto *Bottom = cast<Instruction>(IRB.CreateAShr(Shl, 16));
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auto *Top = cast<Instruction>(IRB.CreateAShr(WideLd, 16));
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BaseUser->replaceUsesOfWith(BaseSExt, Bottom);
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OffsetUser->replaceUsesOfWith(OffsetSExt, Top);
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BaseSExt->eraseFromParent();
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OffsetSExt->eraseFromParent();
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BaseLd->eraseFromParent();
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OffsetLd->eraseFromParent();
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}
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LLVM_DEBUG(dbgs() << "Block after top bottom mul replacements:\n"
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<< *LoopBody << "\n");
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return true;
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}
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// Loop Pass that needs to identify integer add/sub reductions of 16-bit vector
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// multiplications.
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// To use SMLAD:
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@ -658,14 +792,15 @@ bool ARMParallelDSP::MatchSMLAD(Function &F) {
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dbgs() << "Header block:\n"; Header->dump();
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dbgs() << "Loop info:\n\n"; L->dump());
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bool Changed = false;
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ReductionList Reductions;
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MatchReductions(F, L, Header, Reductions);
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if (Reductions.empty())
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return false;
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for (auto &R : Reductions) {
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OpChainList MACCandidates;
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MatchParallelMACSequences(R, MACCandidates);
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if (!CheckMACMemory(MACCandidates))
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if (!CheckMulMemory(MACCandidates))
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continue;
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R.MACCandidates = std::move(MACCandidates);
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@ -682,6 +817,7 @@ bool ARMParallelDSP::MatchSMLAD(Function &F) {
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Instructions Reads, Writes;
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AliasCandidates(Header, Reads, Writes);
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bool Changed = false;
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for (auto &R : Reductions) {
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if (AreAliased(AA, Reads, Writes, R.MACCandidates))
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return false;
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@ -693,15 +829,6 @@ bool ARMParallelDSP::MatchSMLAD(Function &F) {
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return Changed;
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}
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static LoadInst *CreateLoadIns(IRBuilder<NoFolder> &IRB, LoadInst &BaseLoad,
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const Type *LoadTy) {
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const unsigned AddrSpace = BaseLoad.getPointerAddressSpace();
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Value *VecPtr = IRB.CreateBitCast(BaseLoad.getPointerOperand(),
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LoadTy->getPointerTo(AddrSpace));
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return IRB.CreateAlignedLoad(VecPtr, BaseLoad.getAlignment());
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}
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Instruction *ARMParallelDSP::CreateSMLADCall(LoadInst *VecLd0, LoadInst *VecLd1,
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Instruction *Acc, bool Exchange,
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Instruction *InsertAfter) {
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@ -716,8 +843,8 @@ Instruction *ARMParallelDSP::CreateSMLADCall(LoadInst *VecLd0, LoadInst *VecLd1,
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// Replace the reduction chain with an intrinsic call
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const Type *Ty = IntegerType::get(M->getContext(), 32);
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LoadInst *NewLd0 = CreateLoadIns(Builder, VecLd0[0], Ty);
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LoadInst *NewLd1 = CreateLoadIns(Builder, VecLd1[0], Ty);
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LoadInst *NewLd0 = CreateLoadIns(Builder, &VecLd0[0], Ty);
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LoadInst *NewLd1 = CreateLoadIns(Builder, &VecLd1[0], Ty);
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Value* Args[] = { NewLd0, NewLd1, Acc };
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Function *SMLAD = nullptr;
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if (Exchange)
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98
test/CodeGen/ARM/paralleldsp-top-bottom-neg-vec.ll
Normal file
98
test/CodeGen/ARM/paralleldsp-top-bottom-neg-vec.ll
Normal file
@ -0,0 +1,98 @@
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; RUN: opt -mtriple=thumbv7-unknown-linux-android -arm-parallel-dsp -S %s -o - | FileCheck %s
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@a = local_unnamed_addr global i32 0, align 4
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@b = local_unnamed_addr global i8* null, align 4
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@c = local_unnamed_addr global i8 0, align 1
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@d = local_unnamed_addr global i16* null, align 4
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; CHECK-LABEL: @convolve
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; CHECK-NOT: bitcast i16* [[ANY:%[^ ]+]] to i32*
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define void @convolve() local_unnamed_addr #0 {
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entry:
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br label %for.cond
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for.cond:
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%e.0 = phi i32 [ undef, %entry ], [ %e.1.lcssa, %for.end ]
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%f.0 = phi i32 [ undef, %entry ], [ %f.1.lcssa, %for.end ]
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%g.0 = phi i32 [ undef, %entry ], [ %g.1.lcssa, %for.end ]
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%cmp13 = icmp slt i32 %g.0, 1
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br i1 %cmp13, label %for.body.lr.ph, label %for.end
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for.body.lr.ph:
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%0 = load i16*, i16** @d, align 4
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%1 = load i8*, i8** @b, align 4
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%2 = load i32, i32* @a, align 4
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%3 = sub i32 1, %g.0
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%min.iters.check = icmp ugt i32 %3, 3
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%ident.check = icmp eq i32 %2, 1
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%or.cond = and i1 %min.iters.check, %ident.check
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br i1 %or.cond, label %vector.ph, label %for.body.preheader
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vector.ph:
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%n.vec = and i32 %3, -4
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%ind.end = add i32 %g.0, %n.vec
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%4 = mul i32 %2, %n.vec
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%ind.end20 = add i32 %f.0, %4
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%5 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %e.0, i32 0
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br label %vector.body
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vector.body:
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.phi = phi <4 x i32> [ %5, %vector.ph ], [ %14, %vector.body ]
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%offset.idx = add i32 %g.0, %index
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%6 = mul i32 %2, %index
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%offset.idx21 = add i32 %f.0, %6
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%7 = getelementptr inbounds i16, i16* %0, i32 %offset.idx
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%8 = bitcast i16* %7 to <4 x i16>*
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%wide.load = load <4 x i16>, <4 x i16>* %8, align 2
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%9 = sext <4 x i16> %wide.load to <4 x i32>
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%10 = getelementptr inbounds i8, i8* %1, i32 %offset.idx21
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%11 = bitcast i8* %10 to <4 x i8>*
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%wide.load25 = load <4 x i8>, <4 x i8>* %11, align 1
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%12 = zext <4 x i8> %wide.load25 to <4 x i32>
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%13 = mul nsw <4 x i32> %12, %9
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%14 = add nsw <4 x i32> %13, %vec.phi
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%index.next = add i32 %index, 4
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%15 = icmp eq i32 %index.next, %n.vec
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br i1 %15, label %middle.block, label %vector.body
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middle.block:
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%rdx.shuf = shufflevector <4 x i32> %14, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%bin.rdx = add <4 x i32> %14, %rdx.shuf
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%rdx.shuf26 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%bin.rdx27 = add <4 x i32> %bin.rdx, %rdx.shuf26
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%16 = extractelement <4 x i32> %bin.rdx27, i32 0
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%cmp.n = icmp eq i32 %3, %n.vec
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br i1 %cmp.n, label %for.end, label %for.body.preheader
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for.body.preheader:
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%g.116.ph = phi i32 [ %g.0, %for.body.lr.ph ], [ %ind.end, %middle.block ]
|
||||
%f.115.ph = phi i32 [ %f.0, %for.body.lr.ph ], [ %ind.end20, %middle.block ]
|
||||
%e.114.ph = phi i32 [ %e.0, %for.body.lr.ph ], [ %16, %middle.block ]
|
||||
br label %for.body
|
||||
|
||||
for.body:
|
||||
%g.116 = phi i32 [ %inc, %for.body ], [ %g.116.ph, %for.body.preheader ]
|
||||
%f.115 = phi i32 [ %add4, %for.body ], [ %f.115.ph, %for.body.preheader ]
|
||||
%e.114 = phi i32 [ %add, %for.body ], [ %e.114.ph, %for.body.preheader ]
|
||||
%arrayidx = getelementptr inbounds i16, i16* %0, i32 %g.116
|
||||
%17 = load i16, i16* %arrayidx, align 2
|
||||
%conv = sext i16 %17 to i32
|
||||
%arrayidx2 = getelementptr inbounds i8, i8* %1, i32 %f.115
|
||||
%18 = load i8, i8* %arrayidx2, align 1
|
||||
%conv3 = zext i8 %18 to i32
|
||||
%mul = mul nsw i32 %conv3, %conv
|
||||
%add = add nsw i32 %mul, %e.114
|
||||
%inc = add nsw i32 %g.116, 1
|
||||
%add4 = add nsw i32 %2, %f.115
|
||||
%cmp = icmp slt i32 %g.116, 0
|
||||
br i1 %cmp, label %for.body, label %for.end
|
||||
|
||||
for.end:
|
||||
%e.1.lcssa = phi i32 [ %e.0, %for.cond ], [ %16, %middle.block ], [ %add, %for.body ]
|
||||
%f.1.lcssa = phi i32 [ %f.0, %for.cond ], [ %ind.end20, %middle.block ], [ %add4, %for.body ]
|
||||
%g.1.lcssa = phi i32 [ %g.0, %for.cond ], [ %ind.end, %middle.block ], [ %inc, %for.body ]
|
||||
%conv5 = trunc i32 %e.1.lcssa to i8
|
||||
store i8 %conv5, i8* @c, align 1
|
||||
br label %for.cond
|
||||
}
|
||||
209
test/CodeGen/ARM/paralleldsp-top-bottom-neg.ll
Normal file
209
test/CodeGen/ARM/paralleldsp-top-bottom-neg.ll
Normal file
@ -0,0 +1,209 @@
|
||||
; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: topbottom_mul_alias
|
||||
; CHECK-NOT: bitcast i16*
|
||||
define void @topbottom_mul_alias(i32 %N, i32* nocapture readnone %Out, i16* nocapture readonly %In1, i16* nocapture readonly %In2) {
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn1.0 = getelementptr inbounds i16, i16* %In1, i32 %iv
|
||||
%In1.0 = load i16, i16* %PIn1.0, align 2
|
||||
%SIn1.0 = sext i16 %In1.0 to i32
|
||||
%PIn2.0 = getelementptr inbounds i16, i16* %In2, i32 %iv
|
||||
%In2.0 = load i16, i16* %PIn2.0, align 2
|
||||
%SIn2.0 = sext i16 %In2.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %SIn1.0, %SIn2.0
|
||||
%Out.0 = getelementptr inbounds i32, i32* %Out, i32 %iv
|
||||
store i32 %mul5.us.i.i, i32* %Out.0, align 4
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn1.1 = getelementptr inbounds i16, i16* %In1, i32 %iv.1
|
||||
%In1.1 = load i16, i16* %PIn1.1, align 2
|
||||
%SIn1.1 = sext i16 %In1.1 to i32
|
||||
%PIn2.1 = getelementptr inbounds i16, i16* %In2, i32 %iv.1
|
||||
%In2.1 = load i16, i16* %PIn2.1, align 2
|
||||
%SIn2.1 = sext i16 %In2.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %SIn1.1, %SIn2.1
|
||||
%Out.1 = getelementptr inbounds i32, i32* %Out, i32 %iv.1
|
||||
store i32 %mul5.us.i.1.i, i32* %Out.1, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn1.2 = getelementptr inbounds i16, i16* %In1, i32 %iv.2
|
||||
%In1.2 = load i16, i16* %PIn1.2, align 2
|
||||
%SIn1.2 = sext i16 %In1.2 to i32
|
||||
%PIn2.2 = getelementptr inbounds i16, i16* %In2, i32 %iv.2
|
||||
%In2.2 = load i16, i16* %PIn2.2, align 2
|
||||
%SIn2.2 = sext i16 %In2.2 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %SIn1.2, %SIn2.2
|
||||
%Out.2 = getelementptr inbounds i32, i32* %Out, i32 %iv.2
|
||||
store i32 %mul5.us.i.2.i, i32* %Out.2, align 4
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn1.3 = getelementptr inbounds i16, i16* %In1, i32 %iv.3
|
||||
%In1.3 = load i16, i16* %PIn1.3, align 2
|
||||
%SIn1.3 = sext i16 %In1.3 to i32
|
||||
%PIn2.3 = getelementptr inbounds i16, i16* %In2, i32 %iv.3
|
||||
%In2.3 = load i16, i16* %PIn2.3, align 2
|
||||
%SIn2.3 = sext i16 %In2.3 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %SIn1.3, %SIn2.3
|
||||
%Out.3 = getelementptr inbounds i32, i32* %Out, i32 %iv.3
|
||||
store i32 %mul5.us.i.3.i, i32* %Out.3, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; TODO: We should be able to handle this by splatting the const value.
|
||||
; CHECK-LABEL: topbottom_mul_const
|
||||
; CHECK-NOT: bitcast i16*
|
||||
define void @topbottom_mul_const(i32 %N, i32* noalias nocapture readnone %Out, i16* nocapture readonly %In, i16 signext %const) {
|
||||
entry:
|
||||
%conv4.i.i = sext i16 %const to i32
|
||||
br label %for.body
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn.0 = getelementptr inbounds i16, i16* %In, i32 %iv
|
||||
%In.0 = load i16, i16* %PIn.0, align 2
|
||||
%conv.us.i144.i = sext i16 %In.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %conv.us.i144.i, %conv4.i.i
|
||||
%Out.0 = getelementptr inbounds i32, i32* %Out, i32 %iv
|
||||
store i32 %mul5.us.i.i, i32* %Out.0, align 4
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn.1 = getelementptr inbounds i16, i16* %In, i32 %iv.1
|
||||
%In.1 = load i16, i16* %PIn.1, align 2
|
||||
%conv.us.i144.1.i = sext i16 %In.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %conv.us.i144.1.i, %conv4.i.i
|
||||
%Out.1 = getelementptr inbounds i32, i32* %Out, i32 %iv.1
|
||||
store i32 %mul5.us.i.1.i, i32* %Out.1, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn.2 = getelementptr inbounds i16, i16* %In, i32 %iv.2
|
||||
%In.3 = load i16, i16* %PIn.2, align 2
|
||||
%conv.us.i144.2.i = sext i16 %In.3 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %conv.us.i144.2.i, %conv4.i.i
|
||||
%Out.2 = getelementptr inbounds i32, i32* %Out, i32 %iv.2
|
||||
store i32 %mul5.us.i.2.i, i32* %Out.2, align 4
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn.3 = getelementptr inbounds i16, i16* %In, i32 %iv.3
|
||||
%In.4 = load i16, i16* %PIn.3, align 2
|
||||
%conv.us.i144.3.i = sext i16 %In.4 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %conv.us.i144.3.i, %conv4.i.i
|
||||
%Out.3 = getelementptr inbounds i32, i32* %Out, i32 %iv.3
|
||||
store i32 %mul5.us.i.3.i, i32* %Out.3, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; TODO: We should be able to handle this and use smulwt and smulwb.
|
||||
; CHECK-LABEL: topbottom_mul_word_load_const
|
||||
; CHECK-NOT: bitcast i16*
|
||||
define void @topbottom_mul_word_load_const(i32 %N, i32* noalias nocapture readnone %Out, i16* nocapture readonly %In, i32* %C) {
|
||||
entry:
|
||||
%const = load i32, i32* %C
|
||||
br label %for.body
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn.0 = getelementptr inbounds i16, i16* %In, i32 %iv
|
||||
%In.0 = load i16, i16* %PIn.0, align 2
|
||||
%conv.us.i144.i = sext i16 %In.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %conv.us.i144.i, %const
|
||||
%Out.0 = getelementptr inbounds i32, i32* %Out, i32 %iv
|
||||
store i32 %mul5.us.i.i, i32* %Out.0, align 4
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn.1 = getelementptr inbounds i16, i16* %In, i32 %iv.1
|
||||
%In.1 = load i16, i16* %PIn.1, align 2
|
||||
%conv.us.i144.1.i = sext i16 %In.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %conv.us.i144.1.i, %const
|
||||
%Out.1 = getelementptr inbounds i32, i32* %Out, i32 %iv.1
|
||||
store i32 %mul5.us.i.1.i, i32* %Out.1, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn.2 = getelementptr inbounds i16, i16* %In, i32 %iv.2
|
||||
%In.3 = load i16, i16* %PIn.2, align 2
|
||||
%conv.us.i144.2.i = sext i16 %In.3 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %conv.us.i144.2.i, %const
|
||||
%Out.2 = getelementptr inbounds i32, i32* %Out, i32 %iv.2
|
||||
store i32 %mul5.us.i.2.i, i32* %Out.2, align 4
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn.3 = getelementptr inbounds i16, i16* %In, i32 %iv.3
|
||||
%In.4 = load i16, i16* %PIn.3, align 2
|
||||
%conv.us.i144.3.i = sext i16 %In.4 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %conv.us.i144.3.i, %const
|
||||
%Out.3 = getelementptr inbounds i32, i32* %Out, i32 %iv.3
|
||||
store i32 %mul5.us.i.3.i, i32* %Out.3, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: topbottom_mul_8
|
||||
; CHECK-NOT: bitcast i16*
|
||||
define void @topbottom_mul_8(i32 %N, i32* noalias nocapture readnone %Out, i8* nocapture readonly %In1, i8* nocapture readonly %In2) {
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn1.0 = getelementptr inbounds i8, i8* %In1, i32 %iv
|
||||
%In1.0 = load i8, i8* %PIn1.0, align 1
|
||||
%SIn1.0 = sext i8 %In1.0 to i32
|
||||
%PIn2.0 = getelementptr inbounds i8, i8* %In2, i32 %iv
|
||||
%In2.0 = load i8, i8* %PIn2.0, align 1
|
||||
%SIn2.0 = sext i8 %In2.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %SIn1.0, %SIn2.0
|
||||
%Out.0 = getelementptr inbounds i32, i32* %Out, i32 %iv
|
||||
store i32 %mul5.us.i.i, i32* %Out.0, align 4
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn1.1 = getelementptr inbounds i8, i8* %In1, i32 %iv.1
|
||||
%In1.1 = load i8, i8* %PIn1.1, align 1
|
||||
%SIn1.1 = sext i8 %In1.1 to i32
|
||||
%PIn2.1 = getelementptr inbounds i8, i8* %In2, i32 %iv.1
|
||||
%In2.1 = load i8, i8* %PIn2.1, align 1
|
||||
%SIn2.1 = sext i8 %In2.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %SIn1.1, %SIn2.1
|
||||
%Out.1 = getelementptr inbounds i32, i32* %Out, i32 %iv.1
|
||||
store i32 %mul5.us.i.1.i, i32* %Out.1, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn1.2 = getelementptr inbounds i8, i8* %In1, i32 %iv.2
|
||||
%In1.2 = load i8, i8* %PIn1.2, align 1
|
||||
%SIn1.2 = sext i8 %In1.2 to i32
|
||||
%PIn2.2 = getelementptr inbounds i8, i8* %In2, i32 %iv.2
|
||||
%In2.2 = load i8, i8* %PIn2.2, align 1
|
||||
%SIn2.2 = sext i8 %In2.2 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %SIn1.2, %SIn2.2
|
||||
%Out.2 = getelementptr inbounds i32, i32* %Out, i32 %iv.2
|
||||
store i32 %mul5.us.i.2.i, i32* %Out.2, align 4
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn1.3 = getelementptr inbounds i8, i8* %In1, i32 %iv.3
|
||||
%In1.3 = load i8, i8* %PIn1.3, align 1
|
||||
%SIn1.3 = sext i8 %In1.3 to i32
|
||||
%PIn2.3 = getelementptr inbounds i8, i8* %In2, i32 %iv.3
|
||||
%In2.3 = load i8, i8* %PIn2.3, align 1
|
||||
%SIn2.3 = sext i8 %In2.3 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %SIn1.3, %SIn2.3
|
||||
%Out.3 = getelementptr inbounds i32, i32* %Out, i32 %iv.3
|
||||
store i32 %mul5.us.i.3.i, i32* %Out.3, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
251
test/CodeGen/ARM/paralleldsp-top-bottom.ll
Normal file
251
test/CodeGen/ARM/paralleldsp-top-bottom.ll
Normal file
@ -0,0 +1,251 @@
|
||||
; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: topbottom_mul
|
||||
define void @topbottom_mul(i32 %N, i32* noalias nocapture readnone %Out, i16* nocapture readonly %In1, i16* nocapture readonly %In2) {
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
; CHECK: for.body:
|
||||
; CHECK: [[Cast_PIn1_0:%[^ ]+]] = bitcast i16* %PIn1.0 to i32*
|
||||
; CHECK: [[PIn1_01:%[^ ]+]] = load i32, i32* [[Cast_PIn1_0]], align 2
|
||||
; CHECK: [[PIn1_01_shl:%[^ ]+]] = shl i32 [[PIn1_01]], 16
|
||||
; CHECK: [[PIn1_0:%[^ ]+]] = ashr i32 [[PIn1_01_shl]], 16
|
||||
; CHECK: [[PIn1_1:%[^ ]+]] = ashr i32 [[PIn1_01]], 16
|
||||
|
||||
; CHECK: [[Cast_PIn2_0:%[^ ]+]] = bitcast i16* %PIn2.0 to i32*
|
||||
; CHECK: [[PIn2_01:%[^ ]+]] = load i32, i32* [[Cast_PIn2_0]], align 2
|
||||
; CHECK: [[PIn2_01_shl:%[^ ]+]] = shl i32 [[PIn2_01]], 16
|
||||
; CHECK: [[PIn2_0:%[^ ]+]] = ashr i32 [[PIn2_01_shl]], 16
|
||||
; CHECK: [[PIn2_1:%[^ ]+]] = ashr i32 [[PIn2_01]], 16
|
||||
|
||||
; CHECK: mul nsw i32 [[PIn1_0]], [[PIn2_0]]
|
||||
; CHECK: mul nsw i32 [[PIn1_1]], [[PIn2_1]]
|
||||
|
||||
; CHECK: [[Cast_PIn1_2:%[^ ]+]] = bitcast i16* %PIn1.2 to i32*
|
||||
; CHECK: [[PIn1_23:%[^ ]+]] = load i32, i32* [[Cast_PIn1_2]], align 2
|
||||
; CHECK: [[PIn1_23_shl:%[^ ]+]] = shl i32 [[PIn1_23]], 16
|
||||
; CHECK: [[PIn1_2:%[^ ]+]] = ashr i32 [[PIn1_23_shl]], 16
|
||||
; CHECK: [[PIn1_3:%[^ ]+]] = ashr i32 [[PIn1_23]], 16
|
||||
|
||||
; CHECK: [[Cast_PIn2_2:%[^ ]+]] = bitcast i16* %PIn2.2 to i32*
|
||||
; CHECK: [[PIn2_23:%[^ ]+]] = load i32, i32* [[Cast_PIn2_2]], align 2
|
||||
; CHECK: [[PIn2_23_shl:%[^ ]+]] = shl i32 [[PIn2_23]], 16
|
||||
; CHECK: [[PIn2_2:%[^ ]+]] = ashr i32 [[PIn2_23_shl]], 16
|
||||
; CHECK: [[PIn2_3:%[^ ]+]] = ashr i32 [[PIn2_23]], 16
|
||||
|
||||
; CHECK: mul nsw i32 [[PIn1_2]], [[PIn2_2]]
|
||||
; CHECK: mul nsw i32 [[PIn1_3]], [[PIn2_3]]
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn1.0 = getelementptr inbounds i16, i16* %In1, i32 %iv
|
||||
%In1.0 = load i16, i16* %PIn1.0, align 2
|
||||
%SIn1.0 = sext i16 %In1.0 to i32
|
||||
%PIn2.0 = getelementptr inbounds i16, i16* %In2, i32 %iv
|
||||
%In2.0 = load i16, i16* %PIn2.0, align 2
|
||||
%SIn2.0 = sext i16 %In2.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %SIn1.0, %SIn2.0
|
||||
%Out.0 = getelementptr inbounds i32, i32* %Out, i32 %iv
|
||||
store i32 %mul5.us.i.i, i32* %Out.0, align 4
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn1.1 = getelementptr inbounds i16, i16* %In1, i32 %iv.1
|
||||
%In1.1 = load i16, i16* %PIn1.1, align 2
|
||||
%SIn1.1 = sext i16 %In1.1 to i32
|
||||
%PIn2.1 = getelementptr inbounds i16, i16* %In2, i32 %iv.1
|
||||
%In2.1 = load i16, i16* %PIn2.1, align 2
|
||||
%SIn2.1 = sext i16 %In2.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %SIn1.1, %SIn2.1
|
||||
%Out.1 = getelementptr inbounds i32, i32* %Out, i32 %iv.1
|
||||
store i32 %mul5.us.i.1.i, i32* %Out.1, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn1.2 = getelementptr inbounds i16, i16* %In1, i32 %iv.2
|
||||
%In1.2 = load i16, i16* %PIn1.2, align 2
|
||||
%SIn1.2 = sext i16 %In1.2 to i32
|
||||
%PIn2.2 = getelementptr inbounds i16, i16* %In2, i32 %iv.2
|
||||
%In2.2 = load i16, i16* %PIn2.2, align 2
|
||||
%SIn2.2 = sext i16 %In2.2 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %SIn1.2, %SIn2.2
|
||||
%Out.2 = getelementptr inbounds i32, i32* %Out, i32 %iv.2
|
||||
store i32 %mul5.us.i.2.i, i32* %Out.2, align 4
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn1.3 = getelementptr inbounds i16, i16* %In1, i32 %iv.3
|
||||
%In1.3 = load i16, i16* %PIn1.3, align 2
|
||||
%SIn1.3 = sext i16 %In1.3 to i32
|
||||
%PIn2.3 = getelementptr inbounds i16, i16* %In2, i32 %iv.3
|
||||
%In2.3 = load i16, i16* %PIn2.3, align 2
|
||||
%SIn2.3 = sext i16 %In2.3 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %SIn1.3, %SIn2.3
|
||||
%Out.3 = getelementptr inbounds i32, i32* %Out, i32 %iv.3
|
||||
store i32 %mul5.us.i.3.i, i32* %Out.3, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: topbottom_mul_load_const
|
||||
define void @topbottom_mul_load_const(i32 %N, i32* noalias nocapture readnone %Out, i16* nocapture readonly %In, i16* %C) {
|
||||
entry:
|
||||
%const = load i16, i16* %C
|
||||
%conv4.i.i = sext i16 %const to i32
|
||||
br label %for.body
|
||||
|
||||
; CHECK: for.body:
|
||||
; CHECK: [[Cast_PIn_0:%[^ ]+]] = bitcast i16* %PIn.0 to i32*
|
||||
; CHECK: [[PIn_01:%[^ ]+]] = load i32, i32* [[Cast_PIn_0]], align 2
|
||||
; CHECK: [[PIn_01_shl:%[^ ]+]] = shl i32 [[PIn_01]], 16
|
||||
; CHECK: [[PIn_0:%[^ ]+]] = ashr i32 [[PIn_01_shl]], 16
|
||||
; CHECK: [[PIn_1:%[^ ]+]] = ashr i32 [[PIn_01]], 16
|
||||
|
||||
; CHECK: mul nsw i32 [[PIn_0]], %conv4.i.i
|
||||
; CHECK: mul nsw i32 [[PIn_1]], %conv4.i.i
|
||||
|
||||
; CHECK: [[Cast_PIn_2:%[^ ]+]] = bitcast i16* %PIn.2 to i32*
|
||||
; CHECK: [[PIn_23:%[^ ]+]] = load i32, i32* [[Cast_PIn_2]], align 2
|
||||
; CHECK: [[PIn_23_shl:%[^ ]+]] = shl i32 [[PIn_23]], 16
|
||||
; CHECK: [[PIn_2:%[^ ]+]] = ashr i32 [[PIn_23_shl]], 16
|
||||
; CHECK: [[PIn_3:%[^ ]+]] = ashr i32 [[PIn_23]], 16
|
||||
|
||||
; CHECK: mul nsw i32 [[PIn_2]], %conv4.i.i
|
||||
; CHECK: mul nsw i32 [[PIn_3]], %conv4.i.i
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn.0 = getelementptr inbounds i16, i16* %In, i32 %iv
|
||||
%In.0 = load i16, i16* %PIn.0, align 2
|
||||
%conv.us.i144.i = sext i16 %In.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %conv.us.i144.i, %conv4.i.i
|
||||
%Out.0 = getelementptr inbounds i32, i32* %Out, i32 %iv
|
||||
store i32 %mul5.us.i.i, i32* %Out.0, align 4
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn.1 = getelementptr inbounds i16, i16* %In, i32 %iv.1
|
||||
%In.1 = load i16, i16* %PIn.1, align 2
|
||||
%conv.us.i144.1.i = sext i16 %In.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %conv.us.i144.1.i, %conv4.i.i
|
||||
%Out.1 = getelementptr inbounds i32, i32* %Out, i32 %iv.1
|
||||
store i32 %mul5.us.i.1.i, i32* %Out.1, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn.2 = getelementptr inbounds i16, i16* %In, i32 %iv.2
|
||||
%In.3 = load i16, i16* %PIn.2, align 2
|
||||
%conv.us.i144.2.i = sext i16 %In.3 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %conv.us.i144.2.i, %conv4.i.i
|
||||
%Out.2 = getelementptr inbounds i32, i32* %Out, i32 %iv.2
|
||||
store i32 %mul5.us.i.2.i, i32* %Out.2, align 4
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn.3 = getelementptr inbounds i16, i16* %In, i32 %iv.3
|
||||
%In.4 = load i16, i16* %PIn.3, align 2
|
||||
%conv.us.i144.3.i = sext i16 %In.4 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %conv.us.i144.3.i, %conv4.i.i
|
||||
%Out.3 = getelementptr inbounds i32, i32* %Out, i32 %iv.3
|
||||
store i32 %mul5.us.i.3.i, i32* %Out.3, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: topbottom_mul_64
|
||||
define void @topbottom_mul_64(i32 %N, i64* noalias nocapture readnone %Out, i16* nocapture readonly %In1, i16* nocapture readonly %In2) {
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
; CHECK: for.body:
|
||||
; CHECK: [[Cast_PIn1_0:%[^ ]+]] = bitcast i16* %PIn1.0 to i32*
|
||||
; CHECK: [[PIn1_01:%[^ ]+]] = load i32, i32* [[Cast_PIn1_0]], align 2
|
||||
; CHECK: [[PIn1_01_shl:%[^ ]+]] = shl i32 [[PIn1_01]], 16
|
||||
; CHECK: [[PIn1_0:%[^ ]+]] = ashr i32 [[PIn1_01_shl]], 16
|
||||
; CHECK: [[PIn1_1:%[^ ]+]] = ashr i32 [[PIn1_01]], 16
|
||||
|
||||
; CHECK: [[Cast_PIn2_0:%[^ ]+]] = bitcast i16* %PIn2.0 to i32*
|
||||
; CHECK: [[PIn2_01:%[^ ]+]] = load i32, i32* [[Cast_PIn2_0]], align 2
|
||||
; CHECK: [[PIn2_01_shl:%[^ ]+]] = shl i32 [[PIn2_01]], 16
|
||||
; CHECK: [[PIn2_0:%[^ ]+]] = ashr i32 [[PIn2_01_shl]], 16
|
||||
; CHECK: [[PIn2_1:%[^ ]+]] = ashr i32 [[PIn2_01]], 16
|
||||
|
||||
; CHECK: [[Mul0:%[^ ]+]] = mul nsw i32 [[PIn1_0]], [[PIn2_0]]
|
||||
; CHECK: [[SMul0:%[^ ]+]] = sext i32 [[Mul0]] to i64
|
||||
; CHECK: [[Mul1:%[^ ]+]] = mul nsw i32 [[PIn1_1]], [[PIn2_1]]
|
||||
; CHECK: [[SMul1:%[^ ]+]] = sext i32 [[Mul1]] to i64
|
||||
; CHECK: add i64 [[SMul0]], [[SMul1]]
|
||||
|
||||
; CHECK: [[Cast_PIn1_2:%[^ ]+]] = bitcast i16* %PIn1.2 to i32*
|
||||
; CHECK: [[PIn1_23:%[^ ]+]] = load i32, i32* [[Cast_PIn1_2]], align 2
|
||||
; CHECK: [[PIn1_23_shl:%[^ ]+]] = shl i32 [[PIn1_23]], 16
|
||||
; CHECK: [[PIn1_2:%[^ ]+]] = ashr i32 [[PIn1_23_shl]], 16
|
||||
; CHECK: [[PIn1_3:%[^ ]+]] = ashr i32 [[PIn1_23]], 16
|
||||
|
||||
; CHECK: [[Cast_PIn2_2:%[^ ]+]] = bitcast i16* %PIn2.2 to i32*
|
||||
; CHECK: [[PIn2_23:%[^ ]+]] = load i32, i32* [[Cast_PIn2_2]], align 2
|
||||
; CHECK: [[PIn2_23_shl:%[^ ]+]] = shl i32 [[PIn2_23]], 16
|
||||
; CHECK: [[PIn2_2:%[^ ]+]] = ashr i32 [[PIn2_23_shl]], 16
|
||||
; CHECK: [[PIn2_3:%[^ ]+]] = ashr i32 [[PIn2_23]], 16
|
||||
|
||||
; CHECK: [[Mul2:%[^ ]+]] = mul nsw i32 [[PIn1_2]], [[PIn2_2]]
|
||||
; CHECK: [[SMul2:%[^ ]+]] = sext i32 [[Mul2]] to i64
|
||||
; CHECK: [[Mul3:%[^ ]+]] = mul nsw i32 [[PIn1_3]], [[PIn2_3]]
|
||||
; CHECK: [[SMul3:%[^ ]+]] = sext i32 [[Mul3]] to i64
|
||||
; CHECK: add i64 [[SMul2]], [[SMul3]]
|
||||
|
||||
for.body:
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
|
||||
%iv.out = phi i32 [ 0, %entry] , [ %iv.out.next, %for.body ]
|
||||
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
|
||||
%PIn1.0 = getelementptr inbounds i16, i16* %In1, i32 %iv
|
||||
%In1.0 = load i16, i16* %PIn1.0, align 2
|
||||
%SIn1.0 = sext i16 %In1.0 to i32
|
||||
%PIn2.0 = getelementptr inbounds i16, i16* %In2, i32 %iv
|
||||
%In2.0 = load i16, i16* %PIn2.0, align 2
|
||||
%SIn2.0 = sext i16 %In2.0 to i32
|
||||
%mul5.us.i.i = mul nsw i32 %SIn1.0, %SIn2.0
|
||||
%sext.0 = sext i32 %mul5.us.i.i to i64
|
||||
%iv.1 = or i32 %iv, 1
|
||||
%PIn1.1 = getelementptr inbounds i16, i16* %In1, i32 %iv.1
|
||||
%In1.1 = load i16, i16* %PIn1.1, align 2
|
||||
%SIn1.1 = sext i16 %In1.1 to i32
|
||||
%PIn2.1 = getelementptr inbounds i16, i16* %In2, i32 %iv.1
|
||||
%In2.1 = load i16, i16* %PIn2.1, align 2
|
||||
%SIn2.1 = sext i16 %In2.1 to i32
|
||||
%mul5.us.i.1.i = mul nsw i32 %SIn1.1, %SIn2.1
|
||||
%sext.1 = sext i32 %mul5.us.i.1.i to i64
|
||||
%mac.0 = add i64 %sext.0, %sext.1
|
||||
%Out.0 = getelementptr inbounds i64, i64* %Out, i32 %iv.out
|
||||
store i64 %mac.0, i64* %Out.0, align 4
|
||||
%iv.2 = or i32 %iv, 2
|
||||
%PIn1.2 = getelementptr inbounds i16, i16* %In1, i32 %iv.2
|
||||
%In1.2 = load i16, i16* %PIn1.2, align 2
|
||||
%SIn1.2 = sext i16 %In1.2 to i32
|
||||
%PIn2.2 = getelementptr inbounds i16, i16* %In2, i32 %iv.2
|
||||
%In2.2 = load i16, i16* %PIn2.2, align 2
|
||||
%SIn2.2 = sext i16 %In2.2 to i32
|
||||
%mul5.us.i.2.i = mul nsw i32 %SIn1.2, %SIn2.2
|
||||
%sext.2 = sext i32 %mul5.us.i.2.i to i64
|
||||
%iv.3 = or i32 %iv, 3
|
||||
%PIn1.3 = getelementptr inbounds i16, i16* %In1, i32 %iv.3
|
||||
%In1.3 = load i16, i16* %PIn1.3, align 2
|
||||
%SIn1.3 = sext i16 %In1.3 to i32
|
||||
%PIn2.3 = getelementptr inbounds i16, i16* %In2, i32 %iv.3
|
||||
%In2.3 = load i16, i16* %PIn2.3, align 2
|
||||
%SIn2.3 = sext i16 %In2.3 to i32
|
||||
%mul5.us.i.3.i = mul nsw i32 %SIn1.3, %SIn2.3
|
||||
%sext.3 = sext i32 %mul5.us.i.3.i to i64
|
||||
%mac.1 = add i64 %sext.2, %sext.3
|
||||
%iv.out.1 = or i32 %iv.out, 1
|
||||
%Out.1 = getelementptr inbounds i64, i64* %Out, i32 %iv.out.1
|
||||
store i64 %mac.1, i64* %Out.1, align 4
|
||||
%iv.next = add i32 %iv, 4
|
||||
%iv.out.next = add i32 %iv.out, 2
|
||||
%count.next = add i32 %count, -4
|
||||
%niter375.ncmp.3.i = icmp eq i32 %count.next, 0
|
||||
br i1 %niter375.ncmp.3.i, label %exit, label %for.body
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user