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Sparc: Support PSR, TBR, WIM read/write instructions.
Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
This commit is contained in:
James Y Knight
parent
b92164fff1
commit
b4e7488df5
@ -144,9 +144,9 @@ public:
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rk_FloatReg,
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rk_DoubleReg,
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rk_QuadReg,
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rk_CCReg,
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rk_ASRReg
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rk_Special,
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};
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private:
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enum KindTy {
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k_Token,
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@ -679,7 +679,15 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
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default:
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Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
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break;
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case Sparc::PSR:
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Op = SparcOperand::CreateToken("%psr", S);
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break;
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case Sparc::WIM:
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Op = SparcOperand::CreateToken("%wim", S);
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break;
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case Sparc::TBR:
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Op = SparcOperand::CreateToken("%tbr", S);
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break;
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case Sparc::ICC:
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if (name == "xcc")
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Op = SparcOperand::CreateToken("%xcc", S);
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@ -768,7 +776,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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if (name.equals("y")) {
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RegNo = Sparc::Y;
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RegKind = SparcOperand::rk_ASRReg;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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@ -776,20 +784,38 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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&& !name.substr(3).getAsInteger(10, intVal)
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&& intVal > 0 && intVal < 32) {
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RegNo = ASRRegs[intVal];
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RegKind = SparcOperand::rk_ASRReg;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("icc")) {
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RegNo = Sparc::ICC;
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RegKind = SparcOperand::rk_CCReg;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("psr")) {
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RegNo = Sparc::PSR;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("wim")) {
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RegNo = Sparc::WIM;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("tbr")) {
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RegNo = Sparc::TBR;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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if (name.equals("xcc")) {
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// FIXME:: check 64bit.
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RegNo = Sparc::ICC;
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RegKind = SparcOperand::rk_CCReg;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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@ -799,7 +825,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
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&& intVal < 4) {
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// FIXME: check 64bit and handle %fcc1 - %fcc3
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RegNo = Sparc::FCC0 + intVal;
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RegKind = SparcOperand::rk_CCReg;
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RegKind = SparcOperand::rk_Special;
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return true;
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}
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@ -731,6 +731,24 @@ let rs2 = 0 in
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(outs IntRegs:$rd), (ins ASRRegs:$rs1),
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"rd $rs1, $rd", []>;
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// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
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let Predicates = [HasNoV9] in {
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let rs2 = 0, rs1 = 0, Uses=[PSR] in
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def RDPSR : F3_1<2, 0b101001,
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(outs IntRegs:$rd), (ins),
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"rd %psr, $rd", []>;
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let rs2 = 0, rs1 = 0, Uses=[WIM] in
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def RDWIM : F3_1<2, 0b101010,
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(outs IntRegs:$rd), (ins),
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"rd %wim, $rd", []>;
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let rs2 = 0, rs1 = 0, Uses=[TBR] in
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def RDTBR : F3_1<2, 0b101011,
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(outs IntRegs:$rd), (ins),
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"rd %tbr, $rd", []>;
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}
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// Section B.29 - Write State Register Instructions
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def WRASRrr : F3_1<2, 0b110000,
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(outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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@ -739,6 +757,36 @@ def WRASRri : F3_2<2, 0b110000,
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(outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, $rd", []>;
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// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
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let Predicates = [HasNoV9] in {
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let Defs = [PSR], rd=0 in {
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def WRPSRrr : F3_1<2, 0b110001,
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(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wr $rs1, $rs2, %psr", []>;
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def WRPSRri : F3_2<2, 0b110001,
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(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, %psr", []>;
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}
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let Defs = [WIM], rd=0 in {
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def WRWIMrr : F3_1<2, 0b110010,
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(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wr $rs1, $rs2, %wim", []>;
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def WRWIMri : F3_2<2, 0b110010,
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(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, %wim", []>;
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}
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let Defs = [TBR], rd=0 in {
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def WRTBRrr : F3_1<2, 0b110011,
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(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wr $rs1, $rs2, %tbr", []>;
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def WRTBRri : F3_2<2, 0b110011,
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(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, %tbr", []>;
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}
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}
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3u<2, 0b110100, 0b011000100,
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(outs FPRegs:$rd), (ins FPRegs:$rs2),
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@ -89,6 +89,11 @@ def ASR29 : SparcCtrlReg<29, "ASR29">;
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def ASR30 : SparcCtrlReg<30, "ASR30">;
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def ASR31 : SparcCtrlReg<31, "ASR31">;
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// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
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def PSR : SparcCtrlReg<0, "PSR">;
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def WIM : SparcCtrlReg<0, "WIM">;
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def TBR : SparcCtrlReg<0, "TBR">;
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// Integer registers
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def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
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def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
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34
test/MC/Disassembler/Sparc/sparc-special-registers.txt
Normal file
34
test/MC/Disassembler/Sparc/sparc-special-registers.txt
Normal file
@ -0,0 +1,34 @@
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# RUN: llvm-mc --disassemble %s -triple=sparc-unknown-linux | FileCheck %s
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# CHECK: wr %g1, -2, %y
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0x81 0x80 0x7f 0xfe
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# CHECK: rd %y, %i0
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0xb1 0x40 0x00 0x00
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# CHECK: rd %asr1, %i0
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0xb1 0x40 0x40 0x00
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# CHECK: wr %i0, 5, %y
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0x81 0x86 0x20 0x05
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# CHECK: wr %i0, %i1, %asr15
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0x9f 0x86 0x00 0x19
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# CHECK: rd %psr, %i0
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0xb1 0x48 0x00 0x00
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# CHECK: rd %wim, %i0
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0xb1 0x50 0x00 0x00
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# CHECK: rd %tbr, %i0
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0xb1 0x58 0x00 0x00
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# CHECK: wr %i0, 5, %psr
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0x81 0x8e 0x20 0x05
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# CHECK: wr %i0, 5, %wim
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0x81 0x96 0x20 0x05
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# CHECK: wr %i0, 5, %tbr
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0x81 0x9e 0x20 0x05
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@ -183,9 +183,6 @@
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# CHECK: cmp %g1, -2
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0x80 0xa0 0x7f 0xfe
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# CHECK: wr %g1, -2, %y
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0x81 0x80 0x7f 0xfe
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# CHECK: unimp 12
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0x00 0x00 0x00 0x0c
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@ -201,17 +198,5 @@
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# CHECK: rett %i7+8
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0x81 0xcf 0xe0 0x08
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# CHECK: rd %y, %i0
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0xb1 0x40 0x00 0x00
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# CHECK: rd %asr1, %i0
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0xb1 0x40 0x40 0x00
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# CHECK: wr %i0, 5, %y
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0x81 0x86 0x20 0x05
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# CHECK: wr %i0, %i1, %asr15
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0x9f 0x86 0x00 0x19
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# CHECK: stbar
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0x81 0x43 0xc0 0x00
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@ -15,3 +15,21 @@
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! CHECK: rd %asr15, %g0 ! encoding: [0x81,0x43,0xc0,0x00]
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rd %asr15, %g0
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! CHECK: rd %psr, %i0 ! encoding: [0xb1,0x48,0x00,0x00]
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rd %psr, %i0
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! CHECK: rd %wim, %i0 ! encoding: [0xb1,0x50,0x00,0x00]
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rd %wim, %i0
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! CHECK: rd %tbr, %i0 ! encoding: [0xb1,0x58,0x00,0x00]
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rd %tbr, %i0
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! CHECK: wr %i0, 5, %psr ! encoding: [0x81,0x8e,0x20,0x05]
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wr %i0, 5, %psr
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! CHECK: wr %i0, 5, %wim ! encoding: [0x81,0x96,0x20,0x05]
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wr %i0, 5, %wim
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! CHECK: wr %i0, 5, %tbr ! encoding: [0x81,0x9e,0x20,0x05]
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wr %i0, 5, %tbr
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