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[mips] Rename the LA/LI/DLI TableGen definitions and classes. NFC.

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Summary:
Use more reasonable names for these pseudo-instructions.
As there's only one definition tied to any one of these classes, I named them with abbreviated versions of their respective class' name.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7831

llvm-svn: 231240
This commit is contained in:
Toma Tabacu 2015-03-04 13:01:14 +00:00
parent c838645a84
commit b4f7eabf1c
3 changed files with 17 additions and 16 deletions
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16
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1584,10 +1584,10 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
bool MipsAsmParser::needsExpansion(MCInst &Inst) { bool MipsAsmParser::needsExpansion(MCInst &Inst) {
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case Mips::LoadImm32Reg: case Mips::LoadImm32:
case Mips::LoadAddr32Imm: case Mips::LoadImm64:
case Mips::LoadAddr32Reg: case Mips::LoadAddrImm32:
case Mips::LoadImm64Reg: case Mips::LoadAddrReg32:
case Mips::B_MM_Pseudo: case Mips::B_MM_Pseudo:
case Mips::LWM_MM: case Mips::LWM_MM:
case Mips::SWM_MM: case Mips::SWM_MM:
@ -1603,17 +1603,17 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) { SmallVectorImpl<MCInst> &Instructions) {
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: llvm_unreachable("unimplemented expansion"); default: llvm_unreachable("unimplemented expansion");
case Mips::LoadImm32Reg: case Mips::LoadImm32:
return expandLoadImm(Inst, IDLoc, Instructions); return expandLoadImm(Inst, IDLoc, Instructions);
case Mips::LoadImm64Reg: case Mips::LoadImm64:
if (!isGP64bit()) { if (!isGP64bit()) {
Error(IDLoc, "instruction requires a 64-bit architecture"); Error(IDLoc, "instruction requires a 64-bit architecture");
return true; return true;
} }
return expandLoadImm(Inst, IDLoc, Instructions); return expandLoadImm(Inst, IDLoc, Instructions);
case Mips::LoadAddr32Imm: case Mips::LoadAddrImm32:
return expandLoadAddressImm(Inst, IDLoc, Instructions); return expandLoadAddressImm(Inst, IDLoc, Instructions);
case Mips::LoadAddr32Reg: case Mips::LoadAddrReg32:
return expandLoadAddressReg(Inst, IDLoc, Instructions); return expandLoadAddressReg(Inst, IDLoc, Instructions);
case Mips::B_MM_Pseudo: case Mips::B_MM_Pseudo:
return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions); return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);

4
lib/Target/Mips/Mips64InstrInfo.td
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@ -604,7 +604,7 @@ def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
// Assembler Pseudo Instructions // Assembler Pseudo Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class LoadImm64<string instr_asm, Operand Od, RegisterOperand RO> : class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
!strconcat(instr_asm, "\t$rt, $imm64")> ; !strconcat(instr_asm, "\t$rt, $imm64")> ;
def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>; def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;

13
lib/Target/Mips/MipsInstrInfo.td
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@ -1639,20 +1639,21 @@ def : MipsInstAlias<"sync",
// Assembler Pseudo Instructions // Assembler Pseudo Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class LoadImm32<string instr_asm, Operand Od, RegisterOperand RO> : class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
!strconcat(instr_asm, "\t$rt, $imm32")> ; !strconcat(instr_asm, "\t$rt, $imm32")> ;
def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
!strconcat(instr_asm, "\t$rt, $addr")> ; !strconcat(instr_asm, "\t$rt, $addr")> ;
def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
!strconcat(instr_asm, "\t$rt, $imm32")> ; !strconcat(instr_asm, "\t$rt, $imm32")> ;
def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
"jal\t$rd, $rs"> ; "jal\t$rd, $rs"> ;