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[X86] Correct vfixupimm load patterns to look for an integer load, not a floating point load bitcasted to integer.
DAG combine wouldn't let a floating point load bitcasted to integer exist. It would just be an integer load. llvm-svn: 336626
This commit is contained in:
Craig Topper
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be32016e90
commit
b4fbac048d
@ -90,12 +90,6 @@ class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
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!cast<ComplexPattern>("sse_load_f64"),
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?));
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ValueType IntVT = !cast<ValueType>(
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!if (!eq (!srl(EltSize,5),0),
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VTName,
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!if (!eq(TypeVariantName, "f"),
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"v" # NumElts # "i" # EltSize,
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VTName)));
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// The string to specify embedded broadcast in assembly.
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string BroadcastStr = "{1to" # NumElts # "}";
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@ -11364,14 +11358,15 @@ let Predicates = [HasVLX] in {
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//===----------------------------------------------------------------------===//
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multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86FoldableSchedWrite sched, X86VectorVTInfo _>{
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X86FoldableSchedWrite sched, X86VectorVTInfo _,
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X86VectorVTInfo TblVT>{
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
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defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
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OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
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(OpNode (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(_.IntVT _.RC:$src3),
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(TblVT.VT _.RC:$src3),
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(i32 imm:$src4),
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(i32 FROUND_CURRENT))>, Sched<[sched]>;
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defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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@ -11379,7 +11374,7 @@ multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
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(OpNode (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(_.IntVT (bitconvert (_.LdFrag addr:$src3))),
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(TblVT.VT (bitconvert (TblVT.LdFrag addr:$src3))),
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(i32 imm:$src4),
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(i32 FROUND_CURRENT))>,
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Sched<[sched.Folded, ReadAfterLd]>;
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@ -11389,7 +11384,7 @@ multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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"$src2, ${src3}"##_.BroadcastStr##", $src4",
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(OpNode (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(_.IntVT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
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(TblVT.VT (X86VBroadcast(TblVT.ScalarLdFrag addr:$src3))),
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(i32 imm:$src4),
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(i32 FROUND_CURRENT))>,
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EVEX_B, Sched<[sched.Folded, ReadAfterLd]>;
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@ -11398,7 +11393,7 @@ multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_fixupimm_packed_sae<bits<8> opc, string OpcodeStr,
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SDNode OpNode, X86FoldableSchedWrite sched,
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X86VectorVTInfo _>{
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X86VectorVTInfo _, X86VectorVTInfo TblVT>{
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
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defm rrib : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
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@ -11406,7 +11401,7 @@ let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
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"$src2, $src3, {sae}, $src4",
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(OpNode (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(_.IntVT _.RC:$src3),
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(TblVT.VT _.RC:$src3),
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(i32 imm:$src4),
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(i32 FROUND_NO_EXC))>,
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EVEX_B, Sched<[sched]>;
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@ -11450,17 +11445,21 @@ multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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multiclass avx512_fixupimm_packed_all<X86SchedWriteWidths sched,
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AVX512VLVectorVTInfo _Vec> {
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AVX512VLVectorVTInfo _Vec,
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AVX512VLVectorVTInfo _Tbl> {
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let Predicates = [HasAVX512] in
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defm Z : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.ZMM,
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_Vec.info512>,
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_Vec.info512, _Tbl.info512>,
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avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, sched.ZMM,
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_Vec.info512>, AVX512AIi8Base, EVEX_4V, EVEX_V512;
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_Vec.info512, _Tbl.info512>, AVX512AIi8Base,
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EVEX_4V, EVEX_V512;
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z128 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.XMM,
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_Vec.info128>, AVX512AIi8Base, EVEX_4V, EVEX_V128;
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_Vec.info128, _Tbl.info128>, AVX512AIi8Base,
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EVEX_4V, EVEX_V128;
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defm Z256 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, sched.YMM,
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_Vec.info256>, AVX512AIi8Base, EVEX_4V, EVEX_V256;
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_Vec.info256, _Tbl.info256>, AVX512AIi8Base,
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EVEX_4V, EVEX_V256;
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}
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}
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@ -11470,10 +11469,10 @@ defm VFIXUPIMMSSZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar
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defm VFIXUPIMMSDZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
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SchedWriteFAdd.Scl, f64x_info, v2i64x_info>,
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AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
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defm VFIXUPIMMPS : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f32_info>,
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EVEX_CD8<32, CD8VF>;
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defm VFIXUPIMMPD : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f64_info>,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VFIXUPIMMPS : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f32_info,
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avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
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defm VFIXUPIMMPD : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f64_info,
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avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
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// Patterns used to select SSE scalar fp arithmetic instructions from
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// either:
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@ -4162,8 +4162,7 @@ define <8 x double>@test_int_x86_avx512_mask_fixupimm_pd_512(<8 x double> %x0, <
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define <8 x double>@test_int_x86_avx512_mask_fixupimm_pd_512_load(<8 x double> %x0, <8 x double> %x1, <8 x i64>* %x2ptr) {
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; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_pd_512_load:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vmovapd (%rdi), %zmm2
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; CHECK-NEXT: vfixupimmpd $3, %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: vfixupimmpd $3, (%rdi), %zmm1, %zmm0
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; CHECK-NEXT: retq
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%x2 = load <8 x i64>, <8 x i64>* %x2ptr
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%res = call <8 x double> @llvm.x86.avx512.mask.fixupimm.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x i64> %x2, i32 3, i8 -1, i32 4)
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@ -4265,8 +4264,7 @@ define <16 x float>@test_int_x86_avx512_mask_fixupimm_ps_512(<16 x float> %x0, <
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define <16 x float>@test_int_x86_avx512_mask_fixupimm_ps_512_load(<16 x float> %x0, <16 x float> %x1, <16 x i32>* %x2ptr) {
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; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_ps_512_load:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vmovaps (%rdi), %zmm2
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; CHECK-NEXT: vfixupimmps $5, %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: vfixupimmps $5, (%rdi), %zmm1, %zmm0
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; CHECK-NEXT: retq
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%x2 = load <16 x i32>, <16 x i32>* %x2ptr
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%res = call <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i32 5, i16 -1, i32 4)
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