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MC: correct IMAGE_REL_ARM_MOV32T relocation emission

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This corrects the emission of IMAGE_REL_ARM_MOV32T relocations.  Previously, we
were avoiding the high portion of the relocation too early.  If there was a
section-relative relocation with an offset greater than 16-bits (65535), you
would end up truncating the high order bits of the offset.  Allow the current
relocation representation to flow through out the MC layer to the object writer.
Use the new ability to restrict recorded relocations to avoid emitting the
relocation into the final object.

llvm-svn: 209337
This commit is contained in:
Saleem Abdulrasool 2014-05-21 23:17:56 +00:00
parent 1b56559bfe
commit b55afc349f
3 changed files with 44 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -1029,9 +1029,6 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
switch (ARM16Expr->getKind()) {
default: llvm_unreachable("Unsupported ARMFixup");
case ARMMCExpr::VK_ARM_HI16:
if (Triple(STI.getTargetTriple()).isOSWindows())
return 0;
Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16
: ARM::fixup_arm_movt_hi16);
break;

10
lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
View File

@ -27,6 +27,8 @@ public:
unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsCrossSection) const override;
bool recordRelocation(const MCFixup &) const override;
};
unsigned ARMWinCOFFObjectWriter::getRelocType(const MCValue &Target,
@ -61,12 +63,14 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(const MCValue &Target,
case ARM::fixup_arm_thumb_blx:
return COFF::IMAGE_REL_ARM_BLX23T;
case ARM::fixup_t2_movw_lo16:
return COFF::IMAGE_REL_ARM_MOV32T;
case ARM::fixup_t2_movt_hi16:
llvm_unreachable("High-word for pair-wise relocations are contiguously "
"addressed as an IMAGE_REL_ARM_MOV32T relocation");
return COFF::IMAGE_REL_ARM_MOV32T;
}
}
bool ARMWinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {
return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
}
}
namespace llvm {

37
test/MC/ARM/Windows/mov32t-range.s Normal file
View File

@ -0,0 +1,37 @@
@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
@ RUN: | llvm-readobj -r - | FileCheck -check-prefix CHECK-RELOCATIONS %s
@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
@ RUN: | llvm-objdump -d - | FileCheck -check-prefix CHECK-ENCODING %s
.syntax unified
.thumb
.text
.def truncation
.scl 3
.type 32
.endef
.align 2
.thumb_func
truncation:
movw r0, :lower16:.Lerange
movt r0, :upper16:.Lerange
bx lr
.section .rdata,"rd"
.Lbuffer:
.zero 65536
.Lerange:
.asciz "-erange"
@ CHECK-RELOCATIONS: Relocations [
@ CHECK-RELOCATIONS: .text {
@ CHECK-RELOCATIONS: 0x0 IMAGE_REL_ARM_MOV32T .rdata
@ CHECK-RELOCATIONS-NOT: 0x4 IMAGE_REL_ARM_MOV32T .rdata
@ CHECK-RELOCATIONS: }
@ CHECK-RELOCATIONS: ]
@ CHECK-ENCODING: 0: 40 f2 00 00
@ CHECK-ENCODING-NEXT: 4: c0 f2 01 00