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[NFC] Fixed arm/aarch64 test
llvm-svn: 363049
This commit is contained in:
David Bolvansky
parent
3d3a3945a8
commit
b57c4e067b
@ -1,7 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
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; RUN: llc < %s -mtriple=armv8a -mattr=+neon | FileCheck %s -check-prefix=CHECK-ARM8A-NEON
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define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
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; CHECK-LABEL: cnt32_advsimd:
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@ -28,27 +27,6 @@ define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
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; CHECK-NONEON-NEXT: mul w8, w8, w9
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; CHECK-NONEON-NEXT: lsr w0, w8, #24
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; CHECK-NONEON-NEXT: ret
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;
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; CHECK-ARM8A-NEON-LABEL: cnt32_advsimd:
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; CHECK-ARM8A-NEON: @ %bb.0:
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; CHECK-ARM8A-NEON-NEXT: movw r1, #21845
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; CHECK-ARM8A-NEON-NEXT: movt r1, #21845
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; CHECK-ARM8A-NEON-NEXT: and r1, r1, r0, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #13107
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; CHECK-ARM8A-NEON-NEXT: movt r1, #13107
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; CHECK-ARM8A-NEON-NEXT: and r2, r0, r1
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; CHECK-ARM8A-NEON-NEXT: and r0, r1, r0, lsr #2
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; CHECK-ARM8A-NEON-NEXT: movw r1, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
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; CHECK-ARM8A-NEON-NEXT: movt r1, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
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; CHECK-ARM8A-NEON-NEXT: and r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #257
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; CHECK-ARM8A-NEON-NEXT: movt r1, #257
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; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
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; CHECK-ARM8A-NEON-NEXT: bx lr
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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}
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@ -79,29 +57,6 @@ define i32 @cnt32_advsimd_2(<2 x i32> %x) {
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; CHECK-NONEON-NEXT: mul w8, w8, w9
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; CHECK-NONEON-NEXT: lsr w0, w8, #24
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; CHECK-NONEON-NEXT: ret
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;
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; CHECK-ARM8A-NEON-LABEL: cnt32_advsimd_2:
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; CHECK-ARM8A-NEON: @ %bb.0:
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; CHECK-ARM8A-NEON-NEXT: vmov d16, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #21845
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; CHECK-ARM8A-NEON-NEXT: movt r1, #21845
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; CHECK-ARM8A-NEON-NEXT: vmov.32 r0, d16[0]
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; CHECK-ARM8A-NEON-NEXT: and r1, r1, r0, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #13107
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; CHECK-ARM8A-NEON-NEXT: movt r1, #13107
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; CHECK-ARM8A-NEON-NEXT: and r2, r0, r1
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; CHECK-ARM8A-NEON-NEXT: and r0, r1, r0, lsr #2
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; CHECK-ARM8A-NEON-NEXT: movw r1, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
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; CHECK-ARM8A-NEON-NEXT: movt r1, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
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; CHECK-ARM8A-NEON-NEXT: and r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #257
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; CHECK-ARM8A-NEON-NEXT: movt r1, #257
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; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
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; CHECK-ARM8A-NEON-NEXT: bx lr
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%1 = extractelement <2 x i32> %x, i64 0
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%2 = tail call i32 @llvm.ctpop.i32(i32 %1)
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ret i32 %2
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@ -131,38 +86,6 @@ define i64 @cnt64_advsimd(i64 %x) nounwind readnone {
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; CHECK-NONEON-NEXT: mul x8, x8, x9
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; CHECK-NONEON-NEXT: lsr x0, x8, #56
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; CHECK-NONEON-NEXT: ret
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;
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; CHECK-ARM8A-NEON-LABEL: cnt64_advsimd:
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; CHECK-ARM8A-NEON: @ %bb.0:
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; CHECK-ARM8A-NEON-NEXT: push {r11, lr}
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; CHECK-ARM8A-NEON-NEXT: movw r12, #21845
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; CHECK-ARM8A-NEON-NEXT: movw lr, #3855
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; CHECK-ARM8A-NEON-NEXT: movt r12, #21845
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; CHECK-ARM8A-NEON-NEXT: and r3, r12, r0, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r3
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; CHECK-ARM8A-NEON-NEXT: movw r3, #13107
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; CHECK-ARM8A-NEON-NEXT: movt r3, #13107
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; CHECK-ARM8A-NEON-NEXT: and r2, r0, r3
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; CHECK-ARM8A-NEON-NEXT: and r0, r3, r0, lsr #2
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; CHECK-ARM8A-NEON-NEXT: movt lr, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
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; CHECK-ARM8A-NEON-NEXT: and r2, r12, r1, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r1, r1, r2
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; CHECK-ARM8A-NEON-NEXT: and r2, r1, r3
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
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; CHECK-ARM8A-NEON-NEXT: and r1, r3, r1, lsr #2
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; CHECK-ARM8A-NEON-NEXT: and r0, r0, lr
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; CHECK-ARM8A-NEON-NEXT: add r1, r2, r1
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; CHECK-ARM8A-NEON-NEXT: movw r2, #257
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; CHECK-ARM8A-NEON-NEXT: movt r2, #257
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; CHECK-ARM8A-NEON-NEXT: add r1, r1, r1, lsr #4
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; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r2
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; CHECK-ARM8A-NEON-NEXT: and r1, r1, lr
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; CHECK-ARM8A-NEON-NEXT: mul r1, r1, r2
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; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r1, lsr #24
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; CHECK-ARM8A-NEON-NEXT: mov r1, #0
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; CHECK-ARM8A-NEON-NEXT: pop {r11, pc}
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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}
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@ -202,27 +125,6 @@ define i32 @cnt32(i32 %x) nounwind readnone noimplicitfloat {
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; CHECK-NONEON-NEXT: mul w8, w8, w9
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; CHECK-NONEON-NEXT: lsr w0, w8, #24
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; CHECK-NONEON-NEXT: ret
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;
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; CHECK-ARM8A-NEON-LABEL: cnt32:
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; CHECK-ARM8A-NEON: @ %bb.0:
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; CHECK-ARM8A-NEON-NEXT: movw r1, #21845
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; CHECK-ARM8A-NEON-NEXT: movt r1, #21845
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; CHECK-ARM8A-NEON-NEXT: and r1, r1, r0, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #13107
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; CHECK-ARM8A-NEON-NEXT: movt r1, #13107
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; CHECK-ARM8A-NEON-NEXT: and r2, r0, r1
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; CHECK-ARM8A-NEON-NEXT: and r0, r1, r0, lsr #2
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; CHECK-ARM8A-NEON-NEXT: movw r1, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
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; CHECK-ARM8A-NEON-NEXT: movt r1, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
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; CHECK-ARM8A-NEON-NEXT: and r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: movw r1, #257
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; CHECK-ARM8A-NEON-NEXT: movt r1, #257
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; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
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; CHECK-ARM8A-NEON-NEXT: bx lr
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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}
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@ -259,38 +161,6 @@ define i64 @cnt64(i64 %x) nounwind readnone noimplicitfloat {
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; CHECK-NONEON-NEXT: mul x8, x8, x9
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; CHECK-NONEON-NEXT: lsr x0, x8, #56
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; CHECK-NONEON-NEXT: ret
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;
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; CHECK-ARM8A-NEON-LABEL: cnt64:
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; CHECK-ARM8A-NEON: @ %bb.0:
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; CHECK-ARM8A-NEON-NEXT: push {r11, lr}
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; CHECK-ARM8A-NEON-NEXT: movw r12, #21845
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; CHECK-ARM8A-NEON-NEXT: movw lr, #3855
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; CHECK-ARM8A-NEON-NEXT: movt r12, #21845
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; CHECK-ARM8A-NEON-NEXT: and r3, r12, r0, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r0, r0, r3
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; CHECK-ARM8A-NEON-NEXT: movw r3, #13107
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; CHECK-ARM8A-NEON-NEXT: movt r3, #13107
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; CHECK-ARM8A-NEON-NEXT: and r2, r0, r3
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; CHECK-ARM8A-NEON-NEXT: and r0, r3, r0, lsr #2
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; CHECK-ARM8A-NEON-NEXT: movt lr, #3855
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; CHECK-ARM8A-NEON-NEXT: add r0, r2, r0
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; CHECK-ARM8A-NEON-NEXT: and r2, r12, r1, lsr #1
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; CHECK-ARM8A-NEON-NEXT: sub r1, r1, r2
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; CHECK-ARM8A-NEON-NEXT: and r2, r1, r3
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r0, lsr #4
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; CHECK-ARM8A-NEON-NEXT: and r1, r3, r1, lsr #2
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; CHECK-ARM8A-NEON-NEXT: and r0, r0, lr
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; CHECK-ARM8A-NEON-NEXT: add r1, r2, r1
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; CHECK-ARM8A-NEON-NEXT: movw r2, #257
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; CHECK-ARM8A-NEON-NEXT: movt r2, #257
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; CHECK-ARM8A-NEON-NEXT: add r1, r1, r1, lsr #4
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; CHECK-ARM8A-NEON-NEXT: mul r0, r0, r2
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; CHECK-ARM8A-NEON-NEXT: and r1, r1, lr
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; CHECK-ARM8A-NEON-NEXT: mul r1, r1, r2
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; CHECK-ARM8A-NEON-NEXT: lsr r0, r0, #24
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; CHECK-ARM8A-NEON-NEXT: add r0, r0, r1, lsr #24
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; CHECK-ARM8A-NEON-NEXT: mov r1, #0
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; CHECK-ARM8A-NEON-NEXT: pop {r11, pc}
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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}
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@ -323,20 +193,6 @@ define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
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; CHECK-NONEON-NEXT: cmp x8, #1 // =1
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; CHECK-NONEON-NEXT: cset w0, eq
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; CHECK-NONEON-NEXT: ret
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;
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; CHECK-ARM8A-NEON-LABEL: ctpop_eq_one:
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; CHECK-ARM8A-NEON: @ %bb.0:
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; CHECK-ARM8A-NEON-NEXT: subs r2, r0, #1
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; CHECK-ARM8A-NEON-NEXT: sbc r3, r1, #0
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; CHECK-ARM8A-NEON-NEXT: and r2, r0, r2
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; CHECK-ARM8A-NEON-NEXT: and r3, r1, r3
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; CHECK-ARM8A-NEON-NEXT: orrs r0, r0, r1
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; CHECK-ARM8A-NEON-NEXT: orr r2, r2, r3
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; CHECK-ARM8A-NEON-NEXT: movwne r0, #1
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; CHECK-ARM8A-NEON-NEXT: clz r2, r2
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; CHECK-ARM8A-NEON-NEXT: lsr r2, r2, #5
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; CHECK-ARM8A-NEON-NEXT: and r0, r0, r2
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; CHECK-ARM8A-NEON-NEXT: bx lr
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cmp = icmp eq i64 %count, 1
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%conv = zext i1 %cmp to i32
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@ -281,6 +281,28 @@ define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
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ret <4 x i32> %tmp2
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}
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define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
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; CHECK-LABEL: ctpop_eq_one:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs r2, r0, #1
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; CHECK-NEXT: sbc r3, r1, #0
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; CHECK-NEXT: and r2, r0, r2
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; CHECK-NEXT: and r3, r1, r3
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; CHECK-NEXT: orr r2, r2, r3
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; CHECK-NEXT: rsbs r3, r2, #0
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; CHECK-NEXT: adc r2, r2, r3
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; CHECK-NEXT: orrs r0, r0, r1
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; CHECK-NEXT: movne r0, #1
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; CHECK-NEXT: and r0, r0, r2
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; CHECK-NEXT: mov pc, lr
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cmp = icmp eq i64 %count, 1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
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