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[TargetLowering] Use Align in allowsMisalignedMemoryAccesses.

Browse Source 
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96097
This commit is contained in:
Craig Topper 2021-02-04 19:22:04 -08:00
parent 1471de1de2
commit b58d6a4b20
33 changed files with 61 additions and 67 deletions
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6
include/llvm/Analysis/TargetTransformInfo.h
View File

@ -798,7 +798,7 @@ public:
/// Determine if the target supports unaligned memory accesses.
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
unsigned AddressSpace = 0,
unsigned Alignment = 1,
Align Alignment = Align(1),
bool *Fast = nullptr) const;
/// Return hardware support for population count.
@ -1499,7 +1499,7 @@ public:
virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
unsigned BitWidth,
unsigned AddressSpace,
unsigned Alignment,
Align Alignment,
bool *Fast) = 0;
virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) = 0;
virtual bool haveFastSqrt(Type *Ty) = 0;
@ -1896,7 +1896,7 @@ public:
return Impl.isFPVectorizationPotentiallyUnsafe();
}
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
unsigned AddressSpace, unsigned Alignment,
unsigned AddressSpace, Align Alignment,
bool *Fast) override {
return Impl.allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
Alignment, Fast);

2
include/llvm/Analysis/TargetTransformInfoImpl.h
View File

@ -310,7 +310,7 @@ public:
bool isFPVectorizationPotentiallyUnsafe() const { return false; }
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
unsigned AddressSpace, unsigned Alignment,
unsigned AddressSpace, Align Alignment,
bool *Fast) const {
return false;
}

2
include/llvm/CodeGen/BasicTTIImpl.h
View File

@ -199,7 +199,7 @@ public:
/// \name Scalar TTI Implementations
/// @{
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
unsigned AddressSpace, unsigned Alignment,
unsigned AddressSpace, Align Alignment,
bool *Fast) const {
EVT E = EVT::getIntegerVT(Context, BitWidth);
return getTLI()->allowsMisalignedMemoryAccesses(

2
include/llvm/CodeGen/TargetLowering.h
View File

@ -1611,7 +1611,7 @@ public:
/// helps to ensure that such replacements don't generate code that causes an
/// alignment error (trap) on the target machine.
virtual bool allowsMisalignedMemoryAccesses(
EVT, unsigned AddrSpace = 0, unsigned Align = 1,
EVT, unsigned AddrSpace = 0, Align Alignment = Align(1),
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool * /*Fast*/ = nullptr) const {
return false;

2
lib/Analysis/TargetTransformInfo.cpp
View File

@ -553,7 +553,7 @@ bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
unsigned BitWidth,
unsigned AddressSpace,
unsigned Alignment,
Align Alignment,
bool *Fast) const {
return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
AddressSpace, Alignment, Fast);

4
lib/CodeGen/CodeGenPrepare.cpp
View File

@ -6931,11 +6931,11 @@ class VectorPromoteHelper {
StoreInst *ST = cast<StoreInst>(CombineInst);
unsigned AS = ST->getPointerAddressSpace();
unsigned Align = ST->getAlignment();
Align Alignment = ST->getAlign();
// Check if this store is supported.
if (!TLI.allowsMisalignedMemoryAccesses(
TLI.getValueType(DL, ST->getValueOperand()->getType()), AS,
Align)) {
Alignment)) {
// If this is not supported, there is no way we can combine
// the extract with the store.
return false;

2
lib/CodeGen/GlobalISel/CombinerHelper.cpp
View File

@ -1057,7 +1057,7 @@ static bool findGISelOptimalMemOpLowering(std::vector<LLT> &MemOps,
MVT VT = getMVTForLLT(Ty);
if (NumMemOps && Op.allowOverlap() && NewTySize < Size &&
TLI.allowsMisalignedMemoryAccesses(
VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign().value() : 0,
VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign() : Align(1),
MachineMemOperand::MONone, &Fast) &&
Fast)
TySize = Size;

7
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -194,9 +194,8 @@ bool TargetLowering::findOptimalMemOpLowering(
// equal to DstAlign (or zero).
VT = MVT::i64;
if (Op.isFixedDstAlign())
while (
Op.getDstAlign() < (VT.getSizeInBits() / 8) &&
!allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign().value()))
while (Op.getDstAlign() < (VT.getSizeInBits() / 8) &&
!allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign()))
VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
assert(VT.isInteger());
@ -250,7 +249,7 @@ bool TargetLowering::findOptimalMemOpLowering(
bool Fast;
if (NumMemOps && Op.allowOverlap() && NewVTSize < Size &&
allowsMisalignedMemoryAccesses(
VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign().value() : 1,
VT, DstAS, Op.isFixedDstAlign() ? Op.getDstAlign() : Align(1),
MachineMemOperand::MONone, &Fast) &&
Fast)
VTSize = Size;

3
lib/CodeGen/TargetLoweringBase.cpp
View File

@ -1698,8 +1698,7 @@ bool TargetLoweringBase::allowsMemoryAccessForAlignment(
}
// This is a misaligned access.
return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment.value(), Flags,
Fast);
return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
}
bool TargetLoweringBase::allowsMemoryAccessForAlignment(

14
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -1656,7 +1656,7 @@ MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
}
bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
bool *Fast) const {
if (Subtarget->requiresStrictAlign())
return false;
@ -1670,7 +1670,7 @@ bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
// Code that uses clang vector extensions can mark that it
// wants unaligned accesses to be treated as fast by
// underspecifying alignment to be 1 or 2.
Align <= 2 ||
Alignment <= 2 ||
// Disregard v2i64. Memcpy lowering produces those and splitting
// them regresses performance on micro-benchmarks and olden/bh.
@ -4144,7 +4144,7 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
unsigned AS = StoreNode->getAddressSpace();
Align Alignment = StoreNode->getAlign();
if (Alignment < MemVT.getStoreSize() &&
!allowsMisalignedMemoryAccesses(MemVT, AS, Alignment.value(),
!allowsMisalignedMemoryAccesses(MemVT, AS, Alignment,
StoreNode->getMemOperand()->getFlags(),
nullptr)) {
return scalarizeVectorStore(StoreNode, DAG);
@ -11395,8 +11395,8 @@ EVT AArch64TargetLowering::getOptimalMemOpType(
if (Op.isAligned(AlignCheck))
return true;
bool Fast;
return allowsMisalignedMemoryAccesses(VT, 0, 1, MachineMemOperand::MONone,
&Fast) &&
return allowsMisalignedMemoryAccesses(VT, 0, Align(1),
MachineMemOperand::MONone, &Fast) &&
Fast;
};
@ -11426,8 +11426,8 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
if (Op.isAligned(AlignCheck))
return true;
bool Fast;
return allowsMisalignedMemoryAccesses(VT, 0, 1, MachineMemOperand::MONone,
&Fast) &&
return allowsMisalignedMemoryAccesses(VT, 0, Align(1),
MachineMemOperand::MONone, &Fast) &&
Fast;
};

2
lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -488,7 +488,7 @@ public:
/// Returns true if the target allows unaligned memory accesses of the
/// specified type.
bool allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace = 0, unsigned Align = 1,
EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool *Fast = nullptr) const override;
/// LLT variant.

10
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
View File

@ -2890,9 +2890,8 @@ SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
// Expand unaligned loads earlier than legalization. Due to visitation order
// problems during legalization, the emitted instructions to pack and unpack
// the bytes again are not eliminated in the case of an unaligned copy.
if (!allowsMisalignedMemoryAccesses(VT, AS, Alignment.value(),
LN->getMemOperand()->getFlags(),
&IsFast)) {
if (!allowsMisalignedMemoryAccesses(
VT, AS, Alignment, LN->getMemOperand()->getFlags(), &IsFast)) {
SDValue Ops[2];
if (VT.isVector())
@ -2946,9 +2945,8 @@ SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
// order problems during legalization, the emitted instructions to pack and
// unpack the bytes again are not eliminated in the case of an unaligned
// copy.
if (!allowsMisalignedMemoryAccesses(VT, AS, Alignment.value(),
SN->getMemOperand()->getFlags(),
&IsFast)) {
if (!allowsMisalignedMemoryAccesses(
VT, AS, Alignment, SN->getMemOperand()->getFlags(), &IsFast)) {
if (VT.isVector())
return scalarizeVectorStore(SN, DAG);

6
lib/Target/AMDGPU/R600ISelLowering.cpp
View File

@ -1239,7 +1239,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
Align Alignment = StoreNode->getAlign();
if (Alignment < MemVT.getStoreSize() &&
!allowsMisalignedMemoryAccesses(MemVT, AS, Alignment.value(),
!allowsMisalignedMemoryAccesses(MemVT, AS, Alignment,
StoreNode->getMemOperand()->getFlags(),
nullptr)) {
return expandUnalignedStore(StoreNode, DAG);
@ -1640,7 +1640,7 @@ bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
}
bool R600TargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
bool *IsFast) const {
if (IsFast)
*IsFast = false;
@ -1655,7 +1655,7 @@ bool R600TargetLowering::allowsMisalignedMemoryAccesses(
if (IsFast)
*IsFast = true;
return VT.bitsGT(MVT::i32) && Align % 4 == 0;
return VT.bitsGT(MVT::i32) && Alignment.value() % 4 == 0;
}
static SDValue CompactSwizzlableVector(

2
lib/Target/AMDGPU/R600ISelLowering.h
View File

@ -50,7 +50,7 @@ public:
const SelectionDAG &DAG) const override;
bool allowsMisalignedMemoryAccesses(
EVT VT, unsigned AS, unsigned Align,
EVT VT, unsigned AS, Align Alignment,
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool *IsFast = nullptr) const override;

6
lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -1467,8 +1467,8 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
}
bool SITargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, unsigned Alignment,
MachineMemOperand::Flags Flags, bool *IsFast) const {
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
bool *IsFast) const {
if (IsFast)
*IsFast = false;
@ -1482,7 +1482,7 @@ bool SITargetLowering::allowsMisalignedMemoryAccesses(
}
return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
Align(Alignment), Flags, IsFast);
Alignment, Flags, IsFast);
}
EVT SITargetLowering::getOptimalMemOpType(

2
lib/Target/AMDGPU/SIISelLowering.h
View File

@ -283,7 +283,7 @@ public:
}
bool allowsMisalignedMemoryAccesses(
EVT VT, unsigned AS, unsigned Alignment,
EVT VT, unsigned AS, Align Alignment,
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool *IsFast = nullptr) const override;

6
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -16594,7 +16594,7 @@ bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
}
bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,
unsigned Alignment,
Align Alignment,
MachineMemOperand::Flags,
bool *Fast) const {
// Depends what it gets converted into if the type is weird.
@ -16673,14 +16673,14 @@ EVT ARMTargetLowering::getOptimalMemOpType(
bool Fast;
if (Op.size() >= 16 &&
(Op.isAligned(Align(16)) ||
(allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1,
(allowsMisalignedMemoryAccesses(MVT::v2f64, 0, Align(1),
MachineMemOperand::MONone, &Fast) &&
Fast))) {
return MVT::v2f64;
} else if (Op.size() >= 8 &&
(Op.isAligned(Align(8)) ||
(allowsMisalignedMemoryAccesses(
MVT::f64, 0, 1, MachineMemOperand::MONone, &Fast) &&
MVT::f64, 0, Align(1), MachineMemOperand::MONone, &Fast) &&
Fast))) {
return MVT::f64;
}

2
lib/Target/ARM/ARMISelLowering.h
View File

@ -396,7 +396,7 @@ class VectorType;
/// unaligned memory accesses of the specified type. Returns whether it
/// is "fast" by reference in the second argument.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
unsigned Align,
Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;

4
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -3442,8 +3442,8 @@ bool HexagonTargetLowering::allowsMemoryAccess(
}
bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, unsigned Alignment,
MachineMemOperand::Flags Flags, bool *Fast) const {
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
bool *Fast) const {
MVT SVT = VT.getSimpleVT();
if (Subtarget.isHVXVectorType(SVT, true))
return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);

5
lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -318,8 +318,9 @@ public:
bool *Fast) const override;
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast)
const override;
Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;
/// Returns relocation base for the given PIC jumptable.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)

2
lib/Target/Mips/Mips16ISelLowering.cpp
View File

@ -156,7 +156,7 @@ llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
}
bool Mips16TargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
EVT VT, unsigned, Align, MachineMemOperand::Flags, bool *Fast) const {
return false;
}

2
lib/Target/Mips/Mips16ISelLowering.h
View File

@ -22,7 +22,7 @@ namespace llvm {
const MipsSubtarget &STI);
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
unsigned Align,
Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;

2
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -422,7 +422,7 @@ SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}
bool MipsSETargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
EVT VT, unsigned, Align, MachineMemOperand::Flags, bool *Fast) const {
MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
if (Subtarget.systemSupportsUnalignedAccess()) {

2
lib/Target/Mips/MipsSEISelLowering.h
View File

@ -41,7 +41,7 @@ class TargetRegisterClass;
const TargetRegisterClass *RC);
bool allowsMisalignedMemoryAccesses(
EVT VT, unsigned AS = 0, unsigned Align = 1,
EVT VT, unsigned AS = 0, Align Alignment = Align(1),
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool *Fast = nullptr) const override;

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -15539,9 +15539,7 @@ bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
return isInt<16>(Imm) || isUInt<16>(Imm);
}
bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
unsigned,
unsigned,
bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned, Align,
MachineMemOperand::Flags,
bool *Fast) const {
if (DisablePPCUnaligned)

2
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -961,7 +961,7 @@ namespace llvm {
/// Is unaligned memory access allowed for the given type, and is it fast
/// relative to software emulation.
bool allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, unsigned Align = 1,
EVT VT, unsigned AddrSpace, Align Alignment = Align(1),
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
bool *Fast = nullptr) const override;

2
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -850,7 +850,7 @@ bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
}
bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
EVT VT, unsigned, Align, MachineMemOperand::Flags, bool *Fast) const {
// Unaligned accesses should never be slower than the expanded version.
// We check specifically for aligned accesses in the few cases where
// they are required.

3
lib/Target/SystemZ/SystemZISelLowering.h
View File

@ -435,8 +435,7 @@ public:
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
unsigned AS,
Instruction *I = nullptr) const override;
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
unsigned Align,
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;
bool isTruncateFree(Type *, Type *) const override;

2
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
View File

@ -623,7 +623,7 @@ bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
}
bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
EVT /*VT*/, unsigned /*AddrSpace*/, unsigned /*Align*/,
EVT /*VT*/, unsigned /*AddrSpace*/, Align /*Align*/,
MachineMemOperand::Flags /*Flags*/, bool *Fast) const {
// WebAssembly supports unaligned accesses, though it should be declared
// with the p2align attribute on loads and stores which do so, and there

2
lib/Target/WebAssembly/WebAssemblyISelLowering.h
View File

@ -66,7 +66,7 @@ private:
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
unsigned AS,
Instruction *I = nullptr) const override;
bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -2340,7 +2340,7 @@ bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
}
bool X86TargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned, unsigned Align, MachineMemOperand::Flags Flags,
EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
bool *Fast) const {
if (Fast) {
switch (VT.getSizeInBits()) {
@ -2364,7 +2364,7 @@ bool X86TargetLowering::allowsMisalignedMemoryAccesses(
// well use a regular unaligned vector load.
// We don't have any NT loads pre-SSE41.
if (!!(Flags & MachineMemOperand::MOLoad))
return (Align < 16 || !Subtarget.hasSSE41());
return (Alignment < 16 || !Subtarget.hasSSE41());
return false;
}
// Misaligned accesses of any size are always allowed.

2
lib/Target/X86/X86ISelLowering.h
View File

@ -919,7 +919,7 @@ namespace llvm {
/// Returns true if the target allows unaligned memory accesses of the
/// specified type. Returns whether it is "fast" in the last argument.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;

10
lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
View File

@ -186,7 +186,7 @@ private:
/// Check if this load/store access is misaligned accesses.
bool accessIsMisaligned(unsigned SzInBytes, unsigned AddressSpace,
unsigned Alignment);
Align Alignment);
};
class LoadStoreVectorizerLegacyPass : public FunctionPass {
@ -1061,7 +1061,7 @@ bool Vectorizer::vectorizeStoreChain(
InstructionsProcessed->insert(Chain.begin(), Chain.end());
// If the store is going to be misaligned, don't vectorize it.
if (accessIsMisaligned(SzInBytes, AS, Alignment.value())) {
if (accessIsMisaligned(SzInBytes, AS, Alignment)) {
if (S0->getPointerAddressSpace() != DL.getAllocaAddrSpace()) {
auto Chains = splitOddVectorElts(Chain, Sz);
return vectorizeStoreChain(Chains.first, InstructionsProcessed) |
@ -1206,7 +1206,7 @@ bool Vectorizer::vectorizeLoadChain(
InstructionsProcessed->insert(Chain.begin(), Chain.end());
// If the load is going to be misaligned, don't vectorize it.
if (accessIsMisaligned(SzInBytes, AS, Alignment.value())) {
if (accessIsMisaligned(SzInBytes, AS, Alignment)) {
if (L0->getPointerAddressSpace() != DL.getAllocaAddrSpace()) {
auto Chains = splitOddVectorElts(Chain, Sz);
return vectorizeLoadChain(Chains.first, InstructionsProcessed) |
@ -1301,8 +1301,8 @@ bool Vectorizer::vectorizeLoadChain(
}
bool Vectorizer::accessIsMisaligned(unsigned SzInBytes, unsigned AddressSpace,
unsigned Alignment) {
if (Alignment % SzInBytes == 0)
Align Alignment) {
if (Alignment.value() % SzInBytes == 0)
return false;
bool Fast = false;