RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Code Issues Projects Releases Wiki Activity

Qualify calls to getTypeForValueType with MVT:: too.

Browse Source 
llvm-svn: 37233
This commit is contained in:
Dan Gohman 2007-05-18 18:41:29 +00:00
parent 1ed1741260
commit b593ad9fb0
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2689,7 +2689,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
getABITypeAlignment(getTypeForValueType(VT));
getABITypeAlignment(MVT::getTypeForValueType(VT));
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
@ -3569,7 +3569,7 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
unsigned Align = ST->getAlignment();
MVT::ValueType SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
getABITypeAlignment(getTypeForValueType(SVT));
getABITypeAlignment(MVT::getTypeForValueType(SVT));
if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
ST->getSrcValueOffset());
@ -3765,7 +3765,7 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
if (VecIn2.Val) {
Ops[1] = VecIn2;
} else {
// Use an undef vbuild_vector as input for the second operand.
// Use an undef vbuild_vector as input for the second operand.
std::vector<SDOperand> UnOps(NumInScalars,
DAG.getNode(ISD::UNDEF,
cast<VTSDNode>(EltType)->getVT()));