mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
AMDGPU/GlobalISel: Basic legalize rules for G_FSHR
Only handles easy 32-bit cases.
This commit is contained in:
Matt Arsenault
parent
5e28cd3473
commit
b5a136377e
@ -3276,6 +3276,8 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
|
||||
case G_FMAXNUM_IEEE:
|
||||
case G_FMINIMUM:
|
||||
case G_FMAXIMUM:
|
||||
case G_FSHL:
|
||||
case G_FSHR:
|
||||
return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
|
||||
case G_SHL:
|
||||
case G_LSHR:
|
||||
|
||||
@ -1313,6 +1313,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
.clampScalar(0, S32, S64)
|
||||
.lower();
|
||||
|
||||
getActionDefinitionsBuilder(G_FSHR)
|
||||
.legalFor({{S32, S32}})
|
||||
.scalarize(0)
|
||||
.lower();
|
||||
|
||||
getActionDefinitionsBuilder(G_READCYCLECOUNTER)
|
||||
.legalFor({S64});
|
||||
|
||||
@ -1327,7 +1332,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
G_SADDO, G_SSUBO,
|
||||
|
||||
// TODO: Implement
|
||||
G_FMINIMUM, G_FMAXIMUM
|
||||
G_FMINIMUM, G_FMAXIMUM,
|
||||
G_FSHL
|
||||
}).lower();
|
||||
|
||||
getActionDefinitionsBuilder({G_VASTART, G_VAARG, G_BRJT, G_JUMP_TABLE,
|
||||
|
||||
@ -3284,6 +3284,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
case AMDGPU::G_FCANONICALIZE:
|
||||
case AMDGPU::G_INTRINSIC_TRUNC:
|
||||
case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar?
|
||||
case AMDGPU::G_FSHR: // TODO: Expand for scalar
|
||||
case AMDGPU::G_AMDGPU_FFBH_U32:
|
||||
case AMDGPU::G_AMDGPU_FMIN_LEGACY:
|
||||
case AMDGPU::G_AMDGPU_FMAX_LEGACY:
|
||||
|
||||
29
test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
Normal file
29
test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
Normal file
@ -0,0 +1,29 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
---
|
||||
|
||||
name: fshr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
; GCN-LABEL: name: fshr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; GCN: [[V_ALIGNBIT_B32_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
|
||||
; GCN: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s32) = COPY $vgpr2
|
||||
%3:vgpr(s32) = G_FSHR %0, %1, %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
|
||||
...
|
||||
299
test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
Normal file
299
test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
Normal file
@ -0,0 +1,299 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s
|
||||
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
|
||||
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
|
||||
|
||||
---
|
||||
name: test_fshr_s32_s32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
; SI-LABEL: name: test_fshr_s32_s32
|
||||
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
|
||||
; SI: $vgpr0 = COPY [[FSHR]](s32)
|
||||
; VI-LABEL: name: test_fshr_s32_s32
|
||||
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
|
||||
; VI: $vgpr0 = COPY [[FSHR]](s32)
|
||||
; GFX9-LABEL: name: test_fshr_s32_s32
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
|
||||
; GFX9: $vgpr0 = COPY [[FSHR]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $vgpr2
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
$vgpr0 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fshr_v2s32_v2s32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||
|
||||
; SI-LABEL: name: test_fshr_v2s32_v2s32
|
||||
; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
|
||||
; SI: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
|
||||
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
||||
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
|
||||
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
|
||||
; SI: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[UV1]], [[UV3]], [[UV5]](s32)
|
||||
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
|
||||
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
; VI-LABEL: name: test_fshr_v2s32_v2s32
|
||||
; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
|
||||
; VI: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
|
||||
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
||||
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
|
||||
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
|
||||
; VI: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[UV1]], [[UV3]], [[UV5]](s32)
|
||||
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
|
||||
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
; GFX9-LABEL: name: test_fshr_v2s32_v2s32
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
|
||||
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
||||
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
|
||||
; GFX9: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
|
||||
; GFX9: [[FSHR1:%[0-9]+]]:_(s32) = G_FSHR [[UV1]], [[UV3]], [[UV5]](s32)
|
||||
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
|
||||
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
|
||||
%2:_(<2 x s32>) = COPY $vgpr4_vgpr5
|
||||
%3:_(<2 x s32>) = G_FSHR %0, %1, %2
|
||||
$vgpr0_vgpr1 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fshr_s16_s16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
; SI-LABEL: name: test_fshr_s16_s16
|
||||
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s16)
|
||||
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
|
||||
; SI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; VI-LABEL: name: test_fshr_s16_s16
|
||||
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s16)
|
||||
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
|
||||
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GFX9-LABEL: name: test_fshr_s16_s16
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s16)
|
||||
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
|
||||
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $vgpr2
|
||||
%3:_(s16) = G_TRUNC %0
|
||||
%4:_(s16) = G_TRUNC %1
|
||||
%5:_(s16) = G_TRUNC %2
|
||||
%6:_(s16) = G_FSHR %3, %4, %5
|
||||
%7:_(s32) = G_ANYEXT %6
|
||||
$vgpr0 = COPY %7
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fshr_v2s16_v2s16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
; SI-LABEL: name: test_fshr_v2s16_v2s16
|
||||
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
||||
; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
|
||||
; SI: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
|
||||
; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
|
||||
; SI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
|
||||
; SI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY2]](<2 x s16>)
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[UV]], [[UV2]], [[UV4]](s16)
|
||||
; SI: [[FSHR1:%[0-9]+]]:_(s16) = G_FSHR [[UV1]], [[UV3]], [[UV5]](s16)
|
||||
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FSHR]](s16), [[FSHR1]](s16)
|
||||
; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
|
||||
; VI-LABEL: name: test_fshr_v2s16_v2s16
|
||||
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
||||
; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
|
||||
; VI: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
|
||||
; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
|
||||
; VI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
|
||||
; VI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY2]](<2 x s16>)
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[UV]], [[UV2]], [[UV4]](s16)
|
||||
; VI: [[FSHR1:%[0-9]+]]:_(s16) = G_FSHR [[UV1]], [[UV3]], [[UV5]](s16)
|
||||
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FSHR]](s16), [[FSHR1]](s16)
|
||||
; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
|
||||
; GFX9-LABEL: name: test_fshr_v2s16_v2s16
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
|
||||
; GFX9: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
|
||||
; GFX9: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
|
||||
; GFX9: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY2]](<2 x s16>)
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[UV]], [[UV2]], [[UV4]](s16)
|
||||
; GFX9: [[FSHR1:%[0-9]+]]:_(s16) = G_FSHR [[UV1]], [[UV3]], [[UV5]](s16)
|
||||
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FSHR]](s16), [[FSHR1]](s16)
|
||||
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
|
||||
%0:_(<2 x s16>) = COPY $vgpr0
|
||||
%1:_(<2 x s16>) = COPY $vgpr1
|
||||
%2:_(<2 x s16>) = COPY $vgpr2
|
||||
%3:_(<2 x s16>) = G_FSHR %0, %1, %2
|
||||
$vgpr0 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fshr_s64_s64
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||
|
||||
; SI-LABEL: name: test_fshr_s64_s64
|
||||
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
|
||||
; SI: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s64)
|
||||
; SI: $vgpr0_vgpr1 = COPY [[FSHR]](s64)
|
||||
; VI-LABEL: name: test_fshr_s64_s64
|
||||
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
|
||||
; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s64)
|
||||
; VI: $vgpr0_vgpr1 = COPY [[FSHR]](s64)
|
||||
; GFX9-LABEL: name: test_fshr_s64_s64
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s64)
|
||||
; GFX9: $vgpr0_vgpr1 = COPY [[FSHR]](s64)
|
||||
%0:_(s64) = COPY $vgpr0_vgpr1
|
||||
%1:_(s64) = COPY $vgpr2_vgpr3
|
||||
%2:_(s64) = COPY $vgpr4_vgpr5
|
||||
%3:_(s64) = G_FSHR %0, %1, %2
|
||||
$vgpr0_vgpr1 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fshr_s8_s8
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
; SI-LABEL: name: test_fshr_s8_s8
|
||||
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; SI: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
|
||||
; SI: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
|
||||
; SI: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s8)
|
||||
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
|
||||
; SI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; VI-LABEL: name: test_fshr_s8_s8
|
||||
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; VI: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
|
||||
; VI: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
|
||||
; VI: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s8)
|
||||
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
|
||||
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GFX9-LABEL: name: test_fshr_s8_s8
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX9: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
|
||||
; GFX9: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
|
||||
; GFX9: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s8)
|
||||
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
|
||||
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $vgpr2
|
||||
%3:_(s8) = G_TRUNC %0
|
||||
%4:_(s8) = G_TRUNC %1
|
||||
%5:_(s8) = G_TRUNC %2
|
||||
%6:_(s8) = G_FSHR %3, %4, %5
|
||||
%7:_(s32) = G_ANYEXT %6
|
||||
$vgpr0 = COPY %7
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fshr_s24_s24
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
|
||||
; SI-LABEL: name: test_fshr_s24_s24
|
||||
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; SI: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[COPY]](s32)
|
||||
; SI: [[TRUNC1:%[0-9]+]]:_(s24) = G_TRUNC [[COPY1]](s32)
|
||||
; SI: [[TRUNC2:%[0-9]+]]:_(s24) = G_TRUNC [[COPY2]](s32)
|
||||
; SI: [[FSHR:%[0-9]+]]:_(s24) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s24)
|
||||
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s24)
|
||||
; SI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; VI-LABEL: name: test_fshr_s24_s24
|
||||
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; VI: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[COPY]](s32)
|
||||
; VI: [[TRUNC1:%[0-9]+]]:_(s24) = G_TRUNC [[COPY1]](s32)
|
||||
; VI: [[TRUNC2:%[0-9]+]]:_(s24) = G_TRUNC [[COPY2]](s32)
|
||||
; VI: [[FSHR:%[0-9]+]]:_(s24) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s24)
|
||||
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s24)
|
||||
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GFX9-LABEL: name: test_fshr_s24_s24
|
||||
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; GFX9: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[COPY]](s32)
|
||||
; GFX9: [[TRUNC1:%[0-9]+]]:_(s24) = G_TRUNC [[COPY1]](s32)
|
||||
; GFX9: [[TRUNC2:%[0-9]+]]:_(s24) = G_TRUNC [[COPY2]](s32)
|
||||
; GFX9: [[FSHR:%[0-9]+]]:_(s24) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s24)
|
||||
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s24)
|
||||
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $vgpr2
|
||||
%3:_(s24) = G_TRUNC %0
|
||||
%4:_(s24) = G_TRUNC %1
|
||||
%5:_(s24) = G_TRUNC %2
|
||||
%6:_(s24) = G_FSHR %3, %4, %5
|
||||
%7:_(s32) = G_ANYEXT %6
|
||||
$vgpr0 = COPY %7
|
||||
...
|
||||
152
test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
Normal file
152
test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
Normal file
@ -0,0 +1,152 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
|
||||
|
||||
---
|
||||
name: fshr_sss
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1, $sgpr2
|
||||
; CHECK-LABEL: name: fshr_sss
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY5]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_vss
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0, $sgpr1
|
||||
; CHECK-LABEL: name: fshr_vss
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY4]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
%2:_(s32) = COPY $sgpr1
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_svs
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $vgpr0, $sgpr1
|
||||
; CHECK-LABEL: name: fshr_svs
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY1]], [[COPY4]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s32) = COPY $sgpr1
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_ssv
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1, $vgpr0
|
||||
; CHECK-LABEL: name: fshr_ssv
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY2]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_vvs
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr0
|
||||
; CHECK-LABEL: name: fshr_vvs
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY3]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $sgpr0
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_vsv
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0, $vgpr1
|
||||
; CHECK-LABEL: name: fshr_vsv
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY2]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr1
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_svv
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $vgpr0, $vgpr1
|
||||
; CHECK-LABEL: name: fshr_svv
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY1]], [[COPY2]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s32) = COPY $vgpr1
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
---
|
||||
name: fshr_vvv
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
; CHECK-LABEL: name: fshr_vvv
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||
; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $vgpr2
|
||||
%3:_(s32) = G_FSHR %0, %1, %2
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user