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AMDGPU: Allow a SGPR for the conditional KILL operand
Patch by: Bas Nieuwenhuizen Just use the _e64 variant if needed. This should be possible as per def : Pat < (int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))), (SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond)) > ; I don't think we can get an immediate for the other operand for which we need the second 32-bit word. https://reviews.llvm.org/D42302 llvm-svn: 323706
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@ -210,65 +210,73 @@ void SIInsertSkips::kill(MachineInstr &MI) {
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switch (MI.getOperand(2).getImm()) {
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case ISD::SETOEQ:
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case ISD::SETEQ:
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Opcode = AMDGPU::V_CMPX_EQ_F32_e32;
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Opcode = AMDGPU::V_CMPX_EQ_F32_e64;
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break;
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case ISD::SETOGT:
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case ISD::SETGT:
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Opcode = AMDGPU::V_CMPX_LT_F32_e32;
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Opcode = AMDGPU::V_CMPX_LT_F32_e64;
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break;
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case ISD::SETOGE:
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case ISD::SETGE:
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Opcode = AMDGPU::V_CMPX_LE_F32_e32;
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Opcode = AMDGPU::V_CMPX_LE_F32_e64;
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break;
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case ISD::SETOLT:
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case ISD::SETLT:
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Opcode = AMDGPU::V_CMPX_GT_F32_e32;
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Opcode = AMDGPU::V_CMPX_GT_F32_e64;
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break;
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case ISD::SETOLE:
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case ISD::SETLE:
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Opcode = AMDGPU::V_CMPX_GE_F32_e32;
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Opcode = AMDGPU::V_CMPX_GE_F32_e64;
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break;
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case ISD::SETONE:
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case ISD::SETNE:
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Opcode = AMDGPU::V_CMPX_LG_F32_e32;
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Opcode = AMDGPU::V_CMPX_LG_F32_e64;
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break;
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case ISD::SETO:
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Opcode = AMDGPU::V_CMPX_O_F32_e32;
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Opcode = AMDGPU::V_CMPX_O_F32_e64;
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break;
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case ISD::SETUO:
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Opcode = AMDGPU::V_CMPX_U_F32_e32;
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Opcode = AMDGPU::V_CMPX_U_F32_e64;
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break;
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case ISD::SETUEQ:
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Opcode = AMDGPU::V_CMPX_NLG_F32_e32;
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Opcode = AMDGPU::V_CMPX_NLG_F32_e64;
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break;
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case ISD::SETUGT:
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Opcode = AMDGPU::V_CMPX_NGE_F32_e32;
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Opcode = AMDGPU::V_CMPX_NGE_F32_e64;
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break;
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case ISD::SETUGE:
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Opcode = AMDGPU::V_CMPX_NGT_F32_e32;
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Opcode = AMDGPU::V_CMPX_NGT_F32_e64;
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break;
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case ISD::SETULT:
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Opcode = AMDGPU::V_CMPX_NLE_F32_e32;
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Opcode = AMDGPU::V_CMPX_NLE_F32_e64;
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break;
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case ISD::SETULE:
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Opcode = AMDGPU::V_CMPX_NLT_F32_e32;
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Opcode = AMDGPU::V_CMPX_NLT_F32_e64;
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break;
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case ISD::SETUNE:
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Opcode = AMDGPU::V_CMPX_NEQ_F32_e32;
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Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;
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break;
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default:
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llvm_unreachable("invalid ISD:SET cond code");
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}
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// TODO: Allow this:
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if (!MI.getOperand(0).isReg() ||
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!TRI->isVGPR(MBB.getParent()->getRegInfo(),
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MI.getOperand(0).getReg()))
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llvm_unreachable("SI_KILL operand should be a VGPR");
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assert(MI.getOperand(0).isReg());
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BuildMI(MBB, &MI, DL, TII->get(Opcode))
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.add(MI.getOperand(1))
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.add(MI.getOperand(0));
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if (TRI->isVGPR(MBB.getParent()->getRegInfo(),
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MI.getOperand(0).getReg())) {
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Opcode = AMDGPU::getVOPe32(Opcode);
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BuildMI(MBB, &MI, DL, TII->get(Opcode))
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.add(MI.getOperand(1))
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.add(MI.getOperand(0));
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} else {
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BuildMI(MBB, &MI, DL, TII->get(Opcode))
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.addReg(AMDGPU::VCC, RegState::Define)
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.addImm(0) // src0 modifiers
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.add(MI.getOperand(1))
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.addImm(0) // src1 modifiers
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.add(MI.getOperand(0))
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.addImm(0); // omod
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}
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break;
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}
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case AMDGPU::SI_KILL_I1_TERMINATOR: {
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@ -234,6 +234,23 @@ define amdgpu_ps void @wqm(float %a) {
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ret void
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}
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; This checks that we use the 64-bit encoding when the operand is a SGPR.
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; SI-LABEL: {{^}}test_sgpr:
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; SI: v_cmpx_ge_f32_e64
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define amdgpu_ps void @test_sgpr(float inreg %a) #0 {
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%c = fcmp ole float %a, 1.000000e+00
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call void @llvm.amdgcn.kill(i1 %c) #1
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ret void
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}
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; SI-LABEL: {{^}}test_non_inline_imm_sgpr:
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; SI-NOT: v_cmpx_ge_f32_e64
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define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {
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%c = fcmp ole float %a, 1.500000e+00
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call void @llvm.amdgcn.kill(i1 %c) #1
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ret void
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}
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declare void @llvm.amdgcn.kill(i1) #0
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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declare i1 @llvm.amdgcn.wqm.vote(i1)
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