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Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use. This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses. llvm-svn: 96255
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@ -85,11 +85,13 @@ public:
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return true;
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}
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/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root and
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/// folding N is profitable.
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virtual
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bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
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/// IsProfitableToFold - Returns true if it's profitable to fold the specific
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/// operand node N of U during instruction selection that starts at Root.
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virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
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/// IsLegalToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root.
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virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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/// to use for this target when scheduling the DAG.
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@ -1341,8 +1341,7 @@ static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
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/// isNonImmUse - Start searching from Root up the DAG to check is Def can
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/// be reached. Return true if that's the case. However, ignore direct uses
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/// by ImmedUse (which would be U in the example illustrated in
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/// IsLegalAndProfitableToFold) and by Root (which can happen in the store
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/// case).
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/// IsLegalToFold) and by Root (which can happen in the store case).
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/// FIXME: to be really generic, we should allow direct use by any node
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/// that is being folded. But realisticly since we only fold loads which
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/// have one non-chain use, we only need to watch out for load/op/store
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@ -1353,11 +1352,17 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
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return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
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}
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/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root and
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/// folding N is profitable.
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bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const {
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/// IsProfitableToFold - Returns true if it's profitable to fold the specific
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/// operand node N of U during instruction selection that starts at Root.
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bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
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SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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return N.hasOneUse();
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}
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/// IsLegalToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root.
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bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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// If Root use can somehow reach N through a path that that doesn't contain
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@ -1411,7 +1416,7 @@ bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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VT = Root->getValueType(Root->getNumValues()-1);
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}
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return !isNonImmUse(Root, N, U);
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return !isNonImmUse(Root, N.getNode(), U);
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}
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SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
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@ -58,6 +58,8 @@ public:
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return "ARM Instruction Selection";
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}
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virtual void InstructionSelect();
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/// getI32Imm - Return a target constant of type i32 with the specified
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/// value.
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inline SDValue getI32Imm(unsigned Imm) {
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@ -65,7 +67,7 @@ public:
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}
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SDNode *Select(SDNode *N);
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virtual void InstructionSelect();
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bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
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SDValue &B, SDValue &C);
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bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
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@ -133,8 +133,7 @@ namespace {
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bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
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bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const;
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bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
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virtual bool
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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@ -336,8 +335,8 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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return false;
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}
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bool MSP430DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const {
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bool MSP430DAGToDAGISel::IsLegalToFold(SDValue N, SDNode *U,
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SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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/// RMW preprocessing creates the following code:
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@ -364,11 +363,11 @@ bool MSP430DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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/// during preprocessing) to determine whether it's legal to introduce such
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/// "cycle" for a moment.
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DenseMap<SDNode*, SDNode*>::const_iterator I = RMWStores.find(Root);
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if (I != RMWStores.end() && I->second == N)
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if (I != RMWStores.end() && I->second == N.getNode())
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return true;
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// Proceed to 'generic' cycle finder code
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return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
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return SelectionDAGISel::IsLegalToFold(N, U, Root);
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}
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@ -656,7 +655,7 @@ SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
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unsigned Opc8, unsigned Opc16) {
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if (N1.getOpcode() == ISD::LOAD &&
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N1.hasOneUse() &&
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IsLegalAndProfitableToFold(N1.getNode(), Op, Op)) {
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IsLegalToFold(N1, Op, Op)) {
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LoadSDNode *LD = cast<LoadSDNode>(N1);
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if (!isValidIndexedLoad(LD))
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return NULL;
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@ -1513,8 +1513,7 @@ bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
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// Direct load operands are folded in binary operations. But before folding
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// verify if this folding is legal. Fold only if it is legal otherwise
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// convert this direct load to a separate memory operation.
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if(ISel->IsLegalAndProfitableToFold(Op.getOperand(0).getNode(),
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Op.getNode(), Op.getNode()))
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if(ISel->IsLegalToFold(Op.getOperand(0), Op.getNode(), Op.getNode()))
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return false;
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else
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MemOp = 0;
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@ -594,8 +594,7 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
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bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
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SDValue &Base, SDValue &Disp, SDValue &Index) {
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if (ISD::isNON_EXTLoad(N.getNode()) &&
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N.hasOneUse() &&
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IsLegalAndProfitableToFold(N.getNode(), P, P))
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IsLegalToFold(N, P, P))
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return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
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return false;
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}
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@ -183,8 +183,9 @@ namespace {
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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virtual
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bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
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virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
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virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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@ -303,11 +304,18 @@ namespace {
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}
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bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const {
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bool
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X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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if (U == Root)
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if (!N.hasOneUse())
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return false;
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if (N.getOpcode() != ISD::LOAD)
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return true;
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// If N is a load, do additional profitability checks.
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if (U == Root) {
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switch (U->getOpcode()) {
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default: break;
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case X86ISD::ADD:
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@ -354,9 +362,17 @@ bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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}
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}
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}
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}
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return true;
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}
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bool X86DAGToDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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// Proceed to 'generic' cycle finder code
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return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
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return SelectionDAGISel::IsLegalToFold(N, U, Root);
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}
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/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
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@ -1311,8 +1327,8 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Op, SDValue Pred,
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InChain = N.getOperand(0).getValue(1);
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if (ISD::isNON_EXTLoad(InChain.getNode()) &&
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InChain.getValue(0).hasOneUse() &&
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N.hasOneUse() &&
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IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op)) {
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IsProfitableToFold(N, Pred.getNode(), Op) &&
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IsLegalToFold(N, Pred.getNode(), Op)) {
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LoadSDNode *LD = cast<LoadSDNode>(InChain);
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if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
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return false;
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@ -1436,8 +1452,8 @@ bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
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SDValue &Index, SDValue &Disp,
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SDValue &Segment) {
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if (ISD::isNON_EXTLoad(N.getNode()) &&
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N.hasOneUse() &&
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IsLegalAndProfitableToFold(N.getNode(), P, P))
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IsProfitableToFold(N, P, P) &&
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IsLegalToFold(N, P, P))
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return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
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return false;
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}
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@ -566,8 +566,11 @@ void PatternCodeEmitter::EmitMatchCode(TreePatternNode *N, TreePatternNode *P,
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if (NodeHasChain)
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OpNo = 1;
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if (!isRoot) {
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// Multiple uses of actual result?
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emitCheck(getValueName(RootName) + ".hasOneUse()");
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// Check if it's profitable to fold the node. e.g. Check for multiple uses
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// of actual result?
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std::string ParentName(RootName.begin(), RootName.end()-1);
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emitCheck("IsProfitableToFold(" + getValueName(RootName) +
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", " + getNodeName(ParentName) + ", N)");
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EmittedUseCheck = true;
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if (NodeHasChain) {
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// If the immediate use can somehow reach this node through another
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@ -597,8 +600,7 @@ void PatternCodeEmitter::EmitMatchCode(TreePatternNode *N, TreePatternNode *P,
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}
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if (NeedCheck) {
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std::string ParentName(RootName.begin(), RootName.end()-1);
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emitCheck("IsLegalAndProfitableToFold(" + getNodeName(RootName) +
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emitCheck("IsLegalToFold(" + getValueName(RootName) +
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", " + getNodeName(ParentName) + ", N)");
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}
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}
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