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Simplify some boolean conditional return statements in AArch64.
http://reviews.llvm.org/D9979 Patch by Richard Thomson (and some conflict resolution by me). llvm-svn: 262266
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@ -207,9 +207,7 @@ bool AArch64AddressTypePromotion::shouldGetThrough(const Instruction *Inst) {
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}
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static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) {
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if (isa<SelectInst>(Inst) && OpIdx == 0)
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return false;
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return true;
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return !(isa<SelectInst>(Inst) && OpIdx == 0);
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}
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bool
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@ -946,10 +946,7 @@ bool AArch64FastISel::isValueAvailable(const Value *V) const {
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return true;
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const auto *I = cast<Instruction>(V);
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if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
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return true;
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return false;
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return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
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}
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bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
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@ -130,9 +130,7 @@ bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
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// Note: currently hasFP() is always true for hasCalls(), but that's an
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// implementation detail of the current code, not a strict requirement,
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// so stay safe here and check both.
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if (MFI->hasCalls() || hasFP(MF) || NumBytes > 128)
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return false;
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return true;
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return !(MFI->hasCalls() || hasFP(MF) || NumBytes > 128);
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}
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/// hasFP - Return true if the specified function should have a dedicated frame
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@ -328,9 +328,7 @@ static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
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bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
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// it hurts if the value is used at least twice, unless we are optimizing
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// for code size.
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if (ForCodeSize || V.hasOneUse())
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return true;
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return false;
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return ForCodeSize || V.hasOneUse();
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}
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/// SelectShiftedRegister - Select a "shifted register" operand. If the value
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@ -797,10 +795,7 @@ bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
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if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
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return false;
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if (isWorthFolding(N))
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return true;
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return false;
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return isWorthFolding(N);
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}
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bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
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@ -2812,9 +2812,7 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization(
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return false;
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if (getTargetMachine().Options.GuaranteedTailCallOpt) {
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if (IsTailCallConvention(CalleeCC) && CCMatch)
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return true;
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return false;
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return IsTailCallConvention(CalleeCC) && CCMatch;
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}
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// Externally-defined functions with weak linkage should not be
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@ -6974,12 +6972,10 @@ bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
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const DataLayout &DL = I->getModule()->getDataLayout();
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EVT VT = getValueType(DL, User->getOperand(0)->getType());
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if (isFMAFasterThanFMulAndFAdd(VT) &&
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isOperationLegalOrCustom(ISD::FMA, VT) &&
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(Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
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return false;
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return true;
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return !(isFMAFasterThanFMulAndFAdd(VT) &&
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isOperationLegalOrCustom(ISD::FMA, VT) &&
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(Options.AllowFPOpFusion == FPOpFusion::Fast ||
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Options.UnsafeFPMath));
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}
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// All 32-bit GPR operations implicitly zero the high-half of the corresponding
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@ -7282,9 +7278,7 @@ EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
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// Same encoding for add/sub, just flip the sign.
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Immed = std::abs(Immed);
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if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
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return true;
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return false;
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return ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0));
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}
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// Integer comparisons are implemented with ADDS/SUBS, so the range of valid
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@ -7341,10 +7335,8 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
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// Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
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if (!AM.Scale || AM.Scale == 1 ||
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(AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
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return true;
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return false;
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return !AM.Scale || AM.Scale == 1 ||
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(AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes);
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}
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int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
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@ -9309,10 +9301,8 @@ bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
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}
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case ISD::Constant:
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case ISD::TargetConstant: {
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if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
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1LL << (width - 1))
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return true;
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return false;
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return std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
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1LL << (width - 1);
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}
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}
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@ -9922,10 +9912,7 @@ bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
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// return instructions to help enable tail call optimizations for this
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// instruction.
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bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
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if (!CI->isTailCall())
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return false;
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return true;
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return CI->isTailCall();
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}
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bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
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@ -285,10 +285,7 @@ static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr,
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// Do not mess with inline asm.
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const CallInst *CI = dyn_cast<const CallInst>(Instr);
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if (CI && isa<const InlineAsm>(CI->getCalledValue()))
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return false;
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return true;
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return !(CI && isa<const InlineAsm>(CI->getCalledValue()));
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}
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/// Check if the given Cst should be converted into
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@ -190,9 +190,7 @@ bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
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// If it's wrong, we'll materialize the constant and still get to the
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// object; it's just suboptimal. Negative offsets use the unscaled
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// load/store instructions, which have a 9-bit signed immediate.
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if (MFI->getLocalFrameSize() < 256)
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return false;
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return true;
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return MFI->getLocalFrameSize() >= 256;
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}
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return false;
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