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[ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores
We were previously using the SelectT2AddrModeImm7 for both normal and narrowing MVE loads/stores. As the narrowing instructions do not accept sp as a register, it makes little sense to optimise a FrameIndex into the load, only to have to recover that later on. This adds a SelectTAddrModeImm7 which does not do that folding, and uses it for narrowing load/store patterns. Differential Revision: https://reviews.llvm.org/D67489 llvm-svn: 372134
This commit is contained in:
David Green
parent
de9c67b409
commit
b62ff560b1
@ -139,6 +139,8 @@ public:
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bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
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SDValue &OffImm);
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bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
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template <unsigned Shift>
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bool SelectTAddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm);
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// Thumb 2 Addressing Modes:
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bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
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@ -1151,6 +1153,28 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
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return false;
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}
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template <unsigned Shift>
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bool ARMDAGToDAGISel::SelectTAddrModeImm7(SDValue N, SDValue &Base,
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SDValue &OffImm) {
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if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), 1 << Shift, -0x7f, 0x80,
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RHSC)) {
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Base = N.getOperand(0);
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if (N.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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OffImm =
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CurDAG->getTargetConstant(RHSC * (1 << Shift), SDLoc(N), MVT::i32);
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return true;
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}
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}
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// Base only.
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Base = N;
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OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Thumb 2 Addressing Modes
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@ -160,7 +160,8 @@ class TMemImm7ShiftOffsetAsmOperand<int shift> : AsmOperandClass {
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let RenderMethod = "addMemImmOffsetOperands";
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}
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class taddrmode_imm7<int shift> : MemOperand {
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class taddrmode_imm7<int shift> : MemOperand,
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ComplexPattern<i32, 2, "SelectTAddrModeImm7<"#shift#">", []> {
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let ParserMatchClass = TMemImm7ShiftOffsetAsmOperand<shift>;
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// They are printed the same way as the T2 imm8 version
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let PrintMethod = "printT2AddrModeImm8Operand<false>";
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@ -5157,12 +5158,12 @@ let MinAlignment = 2 in {
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}
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let Predicates = [HasMVEInt] in {
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def : Pat<(truncstorevi8 (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr),
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(MVE_VSTRB16 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
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def : Pat<(truncstorevi8 (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr),
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(MVE_VSTRB32 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
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def : Pat<(truncstorevi16_align2 (v4i32 MQPR:$val), t2addrmode_imm7<1>:$addr),
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(MVE_VSTRH32 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
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def : Pat<(truncstorevi8 (v8i16 MQPR:$val), taddrmode_imm7<0>:$addr),
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(MVE_VSTRB16 MQPR:$val, taddrmode_imm7<0>:$addr)>;
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def : Pat<(truncstorevi8 (v4i32 MQPR:$val), taddrmode_imm7<0>:$addr),
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(MVE_VSTRB32 MQPR:$val, taddrmode_imm7<0>:$addr)>;
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def : Pat<(truncstorevi16_align2 (v4i32 MQPR:$val), taddrmode_imm7<1>:$addr),
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(MVE_VSTRH32 MQPR:$val, taddrmode_imm7<1>:$addr)>;
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def : Pat<(post_truncstvi8 (v8i16 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
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(MVE_VSTRB16_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
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@ -5204,9 +5205,9 @@ multiclass MVEExtLoad<string DestLanes, string DestElemBits,
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}
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let Predicates = [HasMVEInt] in {
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defm : MVEExtLoad<"4", "32", "8", "B", "", t2addrmode_imm7<0>>;
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defm : MVEExtLoad<"8", "16", "8", "B", "", t2addrmode_imm7<0>>;
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defm : MVEExtLoad<"4", "32", "16", "H", "_align2", t2addrmode_imm7<1>>;
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defm : MVEExtLoad<"4", "32", "8", "B", "", taddrmode_imm7<0>>;
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defm : MVEExtLoad<"8", "16", "8", "B", "", taddrmode_imm7<0>>;
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defm : MVEExtLoad<"4", "32", "16", "H", "_align2", taddrmode_imm7<1>>;
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}
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@ -77,10 +77,9 @@ define arm_aapcs_vfpcc void @vstrh32() {
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vmov.i32 q0, #0x6
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vstrh.32 q0, [r0, #4]
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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@ -101,10 +100,9 @@ define arm_aapcs_vfpcc void @vstrb32() {
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: vmov.i32 q0, #0x6
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vstrb.32 q0, [r0, #6]
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: vmov.i32 q0, #0x6
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; CHECK-NEXT: vstrb.32 q0, [r0, #2]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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@ -125,10 +123,9 @@ define arm_aapcs_vfpcc void @vstrb16() {
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vstrb.16 q0, [r0, #2]
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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@ -212,16 +209,16 @@ entry:
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define arm_aapcs_vfpcc <4 x i16> @vldrh32() {
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; CHECK-LABEL: vldrh32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: mov r4, sp
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl func
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vldrh.u32 q0, [r0, #4]
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; CHECK-NEXT: vldrh.u32 q0, [r4, #4]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%d = alloca [4 x i16], align 2
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%arraydecay = getelementptr inbounds [4 x i16], [4 x i16]* %d, i32 0, i32 0
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@ -235,16 +232,16 @@ entry:
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define arm_aapcs_vfpcc <4 x i8> @vldrb32() {
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; CHECK-LABEL: vldrb32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: add r4, sp, #4
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl func
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vldrb.u32 q0, [r0, #6]
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; CHECK-NEXT: vldrb.u32 q0, [r4, #2]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%d = alloca [4 x i8], align 2
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%arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %d, i32 0, i32 0
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@ -258,16 +255,16 @@ entry:
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define arm_aapcs_vfpcc <8 x i8> @vldrb16() {
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; CHECK-LABEL: vldrb16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: mov r4, sp
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl func
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vldrb.u16 q0, [r0, #2]
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; CHECK-NEXT: vldrb.u16 q0, [r4, #2]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%d = alloca [8 x i8], align 2
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%arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %d, i32 0, i32 0
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