RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
Code Issues Projects Releases Wiki Activity

[ARM] GlobalISel: Support G_AND

Browse Source 
This is identical to the support for the other binary operators:
- widen to s32
- map into GPR
- select ANDrr (via TableGen'erated code)

llvm-svn: 304885
This commit is contained in:
Diana Picus 2017-06-07 09:17:41 +00:00
parent 20ec5bbffb
commit b692b7a557
6 changed files with 172 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMLegalizerInfo.cpp
View File

@ -45,7 +45,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({Op, 1, p0}, Legal);
}
for (unsigned Op : {G_ADD, G_SUB, G_MUL}) {
for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND}) {
for (auto Ty : {s1, s8, s16})
setAction({Op, Ty}, WidenScalar);
setAction({Op, s32}, Legal);

1
lib/Target/ARM/ARMRegisterBankInfo.cpp
View File

@ -221,6 +221,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_ADD:
case G_SUB:
case G_MUL:
case G_AND:
case G_SDIV:
case G_UDIV:
case G_SEXT:

35
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -28,6 +28,8 @@
define void @test_sdiv_s32() #2 { ret void }
define void @test_udiv_s32() #2 { ret void }
define void @test_and_s32() { ret void }
define void @test_load_from_stack() { ret void }
define void @test_load_f32() #0 { ret void }
define void @test_load_f64() #0 { ret void }
@ -783,6 +785,39 @@ body: |
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_and_s32
# CHECK-LABEL: name: test_and_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
# CHECK: id: 0, class: gpr
# CHECK: id: 1, class: gpr
# CHECK: id: 2, class: gpr
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
%2(s32) = G_AND %0, %1
; CHECK: [[VREGRES:%[0-9]+]] = ANDrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized: true

27
test/CodeGen/ARM/GlobalISel/arm-isel.ll
View File

@ -153,6 +153,33 @@ entry:
ret i32 %sum
}
define i8 @test_and_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_and_i8:
; CHECK: and r0, r0, r1
; CHECK: bx lr
entry:
%sum = and i8 %x, %y
ret i8 %sum
}
define i16 @test_and_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_and_i16:
; CHECK: and r0, r0, r1
; CHECK: bx lr
entry:
%sum = and i16 %x, %y
ret i16 %sum
}
define i32 @test_and_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_and_i32:
; CHECK: and r0, r0, r1
; CHECK: bx lr
entry:
%sum = and i32 %x, %y
ret i32 %sum
}
define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
; CHECK-LABEL: test_stack_args_i32:
; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4

80
test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
View File

@ -15,6 +15,10 @@
define void @test_mul_s16() { ret void }
define void @test_mul_s32() { ret void }
define void @test_and_s8() { ret void }
define void @test_and_s16() { ret void }
define void @test_and_s32() { ret void }
define void @test_load_from_stack() { ret void }
define void @test_legal_loads() #0 { ret void }
define void @test_legal_stores() #0 { ret void }
@ -299,6 +303,82 @@ body: |
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_and_s8
# CHECK-LABEL: name: test_and_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
%1(s8) = COPY %r1
%2(s8) = G_AND %0, %1
; G_AND with s8 should widen
; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s8)
BX_RET 14, _, implicit %r0
...
---
name: test_and_s16
# CHECK-LABEL: name: test_and_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
%1(s16) = COPY %r1
%2(s16) = G_AND %0, %1
; G_AND with s16 should widen
; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s16)
BX_RET 14, _, implicit %r0
...
---
name: test_and_s32
# CHECK-LABEL: name: test_and_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_AND %0, %1
; G_AND with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_load_from_stack

28
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -16,6 +16,8 @@
define void @test_sdiv_s32() #1 { ret void }
define void @test_udiv_s32() #1 { ret void }
define void @test_and_s32() { ret void}
define void @test_loads() #0 { ret void }
define void @test_stores() #0 { ret void }
@ -412,6 +414,32 @@ body: |
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_and_s32
# CHECK-LABEL: name: test_and_s32
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = G_AND %0, %1
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_loads