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Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
This commit is contained in:
Bruno Cardoso Lopes
parent
56a82c5ef8
commit
b6afc5168f
@ -6064,7 +6064,7 @@ LLVM</a>.</p>
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<h5>Syntax:</h5>
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<pre>
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declare void @llvm.prefetch(i8* <address>, i32 <rw>, i32 <locality>)
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declare void @llvm.prefetch(i8* <address>, i32 <rw>, i32 <locality>, i32 <cache type>)
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</pre>
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<h5>Overview:</h5>
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@ -6077,8 +6077,10 @@ LLVM</a>.</p>
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<p><tt>address</tt> is the address to be prefetched, <tt>rw</tt> is the
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specifier determining if the fetch should be for a read (0) or write (1),
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and <tt>locality</tt> is a temporal locality specifier ranging from (0) - no
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locality, to (3) - extremely local keep in cache. The <tt>rw</tt>
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and <tt>locality</tt> arguments must be constant integers.</p>
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locality, to (3) - extremely local keep in cache. The <tt>cache type</tt>
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specifies whether the prefetch is performed on the data (1) or instruction (0)
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cache. The <tt>rw</tt>, <tt>locality</tt> and <tt>cache type</tt> arguments
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must be constant integers.</p>
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<h5>Semantics:</h5>
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<p>This intrinsic does not modify the behavior of the program. In particular,
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@ -580,7 +580,8 @@ namespace ISD {
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// PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
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// their first operand. The other operands are the address to prefetch,
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// read / write specifier, and locality specifier.
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// read / write specifier, locality specifier and instruction / data cache
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// specifier.
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PREFETCH,
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// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
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@ -211,7 +211,8 @@ def int_stackrestore : Intrinsic<[], [llvm_ptr_ty]>,
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// however it does conveniently prevent the prefetch from being reordered
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// with respect to nearby accesses to the same memory.
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def int_prefetch : Intrinsic<[],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty],
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[IntrReadWriteArgMem, NoCapture<0>]>;
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def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>;
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@ -197,8 +197,8 @@ def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
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SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
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]>;
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def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch
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SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
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def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
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SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
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]>;
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def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
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@ -4788,15 +4788,16 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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return implVisitAluOverflow(I, ISD::SMULO);
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case Intrinsic::prefetch: {
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SDValue Ops[4];
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SDValue Ops[5];
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unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
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Ops[0] = getRoot();
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Ops[1] = getValue(I.getArgOperand(0));
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Ops[2] = getValue(I.getArgOperand(1));
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Ops[3] = getValue(I.getArgOperand(2));
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Ops[4] = getValue(I.getArgOperand(3));
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DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
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DAG.getVTList(MVT::Other),
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&Ops[0], 4,
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&Ops[0], 5,
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EVT::getIntegerVT(*Context, 8),
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MachinePointerInfo(I.getArgOperand(0)),
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0, /* align */
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@ -2281,12 +2281,13 @@ static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
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// ARMv7 with MP extension has PLDW.
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return Op.getOperand(0);
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if (Subtarget->isThumb())
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unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
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if (Subtarget->isThumb()) {
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// Invert the bits.
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isRead = ~isRead & 1;
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unsigned isData = Subtarget->isThumb() ? 0 : 1;
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isData = ~isData & 1;
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}
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// Currently there is no intrinsic that matches pli.
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return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
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Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
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DAG.getConstant(isData, MVT::i32));
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@ -62,6 +62,9 @@ def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
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SDTCisInt<1>]>;
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def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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@ -130,7 +133,7 @@ def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
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[SDNPHasChain]>;
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def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
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[SDNPHasChain]>;
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def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
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def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
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[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
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def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
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@ -2006,13 +2006,13 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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// Prefetch intrinsic.
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def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
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"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
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"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
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def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
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"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
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"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
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def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
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"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
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"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
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def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
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// Load, store, and memory fence
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
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@ -284,6 +284,30 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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break;
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}
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// This upgrades the llvm.prefetch intrinsic to accept one more parameter,
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// which is a instruction / data cache identifier. The old version only
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// implicitly accepted the data version.
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if (Name.compare(5,8,"prefetch",8) == 0) {
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// Don't do anything if it has the correct number of arguments already
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if (FTy->getNumParams() == 4)
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break;
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assert(FTy->getNumParams() == 3 && "old prefetch takes 3 args!");
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// We first need to change the name of the old (bad) intrinsic, because
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// its type is incorrect, but we cannot overload that name. We
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// arbitrarily unique it here allowing us to construct a correctly named
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// and typed function below.
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F->setName("");
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NewFn = cast<Function>(M->getOrInsertFunction(Name,
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FTy->getReturnType(),
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FTy->getParamType(0),
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FTy->getParamType(1),
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FTy->getParamType(2),
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FTy->getParamType(2),
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(Type*)0));
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return true;
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}
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break;
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case 'x':
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// This fixes the poorly named crc32 intrinsics
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@ -1344,6 +1368,29 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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CI->eraseFromParent();
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break;
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}
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case Intrinsic::prefetch: {
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IRBuilder<> Builder(C);
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Builder.SetInsertPoint(CI->getParent(), CI);
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const llvm::Type *I32Ty = llvm::Type::getInt32Ty(CI->getContext());
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// Add the extra "data cache" argument
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Value *Operands[4] = { CI->getArgOperand(0), CI->getArgOperand(1),
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CI->getArgOperand(2),
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llvm::ConstantInt::get(I32Ty, 1) };
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CallInst *NewCI = CallInst::Create(NewFn, Operands, Operands+4,
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CI->getName(), CI);
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NewCI->setTailCall(CI->isTailCall());
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NewCI->setCallingConv(CI->getCallingConv());
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// Handle any uses of the old CallInst.
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if (!CI->use_empty())
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// Replace all uses of the old call with the new cast which has the
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// correct type.
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CI->replaceAllUsesWith(NewCI);
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// Clean up the old call now that it has been completely upgraded.
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CI->eraseFromParent();
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break;
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}
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}
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}
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@ -109,3 +109,11 @@ define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D) {
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call void @llvm.x86.sse2.movnt.i(i8* %B, i32 %D)
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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define void @p(i8* %ptr) {
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; CHECK: llvm.prefetch(i8* %ptr, i32 0, i32 1, i32 1)
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tail call void @llvm.prefetch(i8* %ptr, i32 0, i32 1)
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ret void
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}
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@ -17,8 +17,8 @@ entry:
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; THUMB2: t1:
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; THUMB2-NOT: pldw [r0]
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; THUMB2: pld [r0]
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
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ret void
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}
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@ -30,7 +30,7 @@ entry:
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; THUMB2: t2:
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; THUMB2: pld [r0, #1023]
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%tmp = getelementptr i8* %ptr, i32 1023
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tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 )
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tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
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ret void
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}
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@ -45,7 +45,7 @@ entry:
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
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ret void
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}
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@ -59,8 +59,8 @@ entry:
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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@ -6,11 +6,11 @@ entry:
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; CHECK: prefetcht1
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; CHECK: prefetcht0
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; CHECK: prefetchnta
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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