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[PowerPC] Set the innermost hot loop to align 32 bytes
Summary: If the nested loop is an innermost loop, prefer to a 32-byte alignment, so that we can decrease cache misses and branch-prediction misses. Actual alignment of the loop will depend on the hotness check and other logic in alignBlocks. The old code will only align hot loop to 32 bytes when the LoopSize larger than 16 bytes and smaller than 32 bytes, this patch will align the innermost hot loop to 32 bytes not only for the hot loop whose size is 16~32 bytes. Reviewed By: steven.zhang, jsji Differential Revision: https://reviews.llvm.org/D61228 llvm-svn: 363495
This commit is contained in:
Kang Zhang
parent
ed940af216
commit
b6bd9f2f91
@ -113,6 +113,9 @@ cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
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static cl::opt<bool> DisableSCO("disable-ppc-sco",
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cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
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static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
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cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
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static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
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cl::desc("enable quad precision float support on ppc"), cl::Hidden);
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@ -13843,6 +13846,15 @@ unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
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if (!ML)
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break;
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if (!DisableInnermostLoopAlign32) {
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// If the nested loop is an innermost loop, prefer to a 32-byte alignment,
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// so that we can decrease cache misses and branch-prediction misses.
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// Actual alignment of the loop will depend on the hotness check and other
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// logic in alignBlocks.
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if (ML->getLoopDepth() > 1 && ML->getSubLoops().empty())
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return 5;
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}
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const PPCInstrInfo *TII = Subtarget.getInstrInfo();
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// For small loops (between 5 and 8 instructions), align to a 32-byte
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209
test/CodeGen/PowerPC/loop-align.ll
Normal file
209
test/CodeGen/PowerPC/loop-align.ll
Normal file
@ -0,0 +1,209 @@
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; Test the loop alignment.
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; RUN: llc -verify-machineinstrs -mcpu=a2 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,GENERIC
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; Test the loop alignment and the option -disable-ppc-innermost-loop-align32.
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; RUN: llc -verify-machineinstrs -mcpu=a2 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -disable-ppc-innermost-loop-align32 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -disable-ppc-innermost-loop-align32 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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%struct.parm = type { i32*, i32, i32 }
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; Test the loop alignment when the innermost hot loop has more than 8 instructions.
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define void @big_loop(%struct.parm* %arg) {
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entry:
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%localArg.sroa.0.0..sroa_idx = getelementptr inbounds %struct.parm, %struct.parm* %arg, i64 0, i32 0
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%localArg.sroa.0.0.copyload = load i32*, i32** %localArg.sroa.0.0..sroa_idx, align 8
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%localArg.sroa.4.0..sroa_idx56 = getelementptr inbounds %struct.parm, %struct.parm* %arg, i64 0, i32 1
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%localArg.sroa.4.0.copyload = load i32, i32* %localArg.sroa.4.0..sroa_idx56, align 8
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%localArg.sroa.5.0..sroa_idx58 = getelementptr inbounds %struct.parm, %struct.parm* %arg, i64 0, i32 2
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%localArg.sroa.5.0.copyload = load i32, i32* %localArg.sroa.5.0..sroa_idx58, align 4
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%0 = sext i32 %localArg.sroa.5.0.copyload to i64
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br label %do.body
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do.body: ; preds = %do.end, %entry
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%m.0 = phi i32 [ %localArg.sroa.4.0.copyload, %entry ], [ %dec24, %do.end ]
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br label %do.body3
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do.body3: ; preds = %do.body3, %do.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %do.body3 ], [ %0, %do.body ]
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%1 = add nsw i64 %indvars.iv, 2
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%arrayidx = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %1
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%2 = add nsw i64 %indvars.iv, 3
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%3 = trunc i64 %1 to i32
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%4 = add nsw i64 %indvars.iv, 4
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%arrayidx10 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %2
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%5 = trunc i64 %2 to i32
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store i32 %5, i32* %arrayidx10, align 4
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%arrayidx12 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %4
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%6 = trunc i64 %4 to i32
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store i32 %6, i32* %arrayidx12, align 4
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store i32 %3, i32* %arrayidx, align 4
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%arrayidx21 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %indvars.iv
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%7 = trunc i64 %indvars.iv to i32
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%8 = add i32 %7, 1
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store i32 %8, i32* %arrayidx21, align 4
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%indvars.iv.next = add nsw i64 %indvars.iv, -1
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%9 = icmp eq i64 %indvars.iv, 0
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br i1 %9, label %do.end, label %do.body3
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do.end: ; preds = %do.body3
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%dec24 = add nsw i32 %m.0, -1
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%tobool25 = icmp eq i32 %m.0, 0
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br i1 %tobool25, label %do.end26, label %do.body
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do.end26: ; preds = %do.end
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%arrayidx28 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %0
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store i32 0, i32* %arrayidx28, align 4
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ret void
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; CHECK-LABEL: @big_loop
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; CHECK: mtctr
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; GENERIC: .p2align 4
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; PWR: .p2align 5
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; GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; CHECK: bdnz
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}
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; Test the loop alignment when the innermost hot loop has 5-8 instructions.
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define void @general_loop(i32* %s, i64 %m) {
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entry:
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%tobool40 = icmp eq i64 %m, 0
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br i1 %tobool40, label %while.end18, label %while.body3.lr.ph
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while.cond.loopexit: ; preds = %while.body3
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%tobool = icmp eq i64 %dec, 0
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br i1 %tobool, label %while.end18, label %while.body3.lr.ph
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while.body3.lr.ph: ; preds = %entry, %while.cond.loopexit
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%m.addr.041 = phi i64 [ %dec, %while.cond.loopexit ], [ %m, %entry ]
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%dec = add nsw i64 %m.addr.041, -1
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%conv = trunc i64 %m.addr.041 to i32
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%conv11 = trunc i64 %dec to i32
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br label %while.body3
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while.body3: ; preds = %while.body3.lr.ph, %while.body3
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%n.039 = phi i64 [ %m.addr.041, %while.body3.lr.ph ], [ %dec16, %while.body3 ]
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%inc = add nsw i64 %n.039, 1
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%arrayidx = getelementptr inbounds i32, i32* %s, i64 %n.039
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%inc5 = add nsw i64 %n.039, 2
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%arrayidx6 = getelementptr inbounds i32, i32* %s, i64 %inc
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%sub = sub nsw i64 %dec, %inc5
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%conv7 = trunc i64 %sub to i32
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%arrayidx9 = getelementptr inbounds i32, i32* %s, i64 %inc5
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store i32 %conv7, i32* %arrayidx9, align 4
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store i32 %conv11, i32* %arrayidx6, align 4
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store i32 %conv, i32* %arrayidx, align 4
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%dec16 = add nsw i64 %n.039, -1
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%tobool2 = icmp eq i64 %dec16, 0
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br i1 %tobool2, label %while.cond.loopexit, label %while.body3
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while.end18: ; preds = %while.cond.loopexit, %entry
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ret void
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; CHECK-LABEL: @general_loop
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; CHECK: mtctr
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; GENERIC: .p2align 4
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; PWR: .p2align 5
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; GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 5
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; CHECK: bdnz
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}
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; Test the small loop alignment when the innermost hot loop has less than 4 instructions.
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define void @small_loop(i64 %m) {
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entry:
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br label %do.body
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do.body: ; preds = %do.end, %entry
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%m.addr.0 = phi i64 [ %m, %entry ], [ %1, %do.end ]
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br label %do.body1
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do.body1: ; preds = %do.body1, %do.body
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%n.0 = phi i64 [ %m.addr.0, %do.body ], [ %0, %do.body1 ]
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%0 = tail call i64 asm "subi $0,$0,1", "=r,0"(i64 %n.0)
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%tobool = icmp eq i64 %0, 0
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br i1 %tobool, label %do.end, label %do.body1
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do.end: ; preds = %do.body1
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%1 = tail call i64 asm "subi $1,$1,1", "=r,0"(i64 %m.addr.0)
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%tobool3 = icmp eq i64 %1, 0
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br i1 %tobool3, label %do.end4, label %do.body
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do.end4: ; preds = %do.end
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ret void
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; CHECK-LABEL: @small_loop
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; CHECK: mr
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; GENERIC: .p2align 4
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; PWR: .p2align 5
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; GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; CHECK: bne
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}
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; Test the loop alignment when the innermost cold loop has more than 8 instructions.
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define void @big_loop_cold_innerloop(%struct.parm* %arg) {
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entry:
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%localArg.sroa.0.0..sroa_idx = getelementptr inbounds %struct.parm, %struct.parm* %arg, i64 0, i32 0
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%localArg.sroa.0.0.copyload = load i32*, i32** %localArg.sroa.0.0..sroa_idx, align 8
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%localArg.sroa.4.0..sroa_idx56 = getelementptr inbounds %struct.parm, %struct.parm* %arg, i64 0, i32 1
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%localArg.sroa.4.0.copyload = load i32, i32* %localArg.sroa.4.0..sroa_idx56, align 8
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%localArg.sroa.5.0..sroa_idx58 = getelementptr inbounds %struct.parm, %struct.parm* %arg, i64 0, i32 2
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%localArg.sroa.5.0.copyload = load i32, i32* %localArg.sroa.5.0..sroa_idx58, align 4
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%0 = sext i32 %localArg.sroa.5.0.copyload to i64
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br label %do.body
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do.body: ; preds = %do.end, %entry
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%m.0 = phi i32 [ %localArg.sroa.4.0.copyload, %entry ], [ %dec24, %do.end ]
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br label %do.body3
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do.body3: ; preds = %do.body3, %do.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %do.body3 ], [ %0, %do.body ]
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%1 = add nsw i64 %indvars.iv, 2
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%arrayidx = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %1
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%2 = add nsw i64 %indvars.iv, 3
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%3 = trunc i64 %1 to i32
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%4 = add nsw i64 %indvars.iv, 4
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%arrayidx10 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %2
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%5 = trunc i64 %2 to i32
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store i32 %5, i32* %arrayidx10, align 4
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%arrayidx12 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %4
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%6 = trunc i64 %4 to i32
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store i32 %6, i32* %arrayidx12, align 4
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store i32 %3, i32* %arrayidx, align 4
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%arrayidx21 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %indvars.iv
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%7 = trunc i64 %indvars.iv to i32
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%8 = add i32 %7, 1
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store i32 %8, i32* %arrayidx21, align 4
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%indvars.iv.next = add nsw i64 %indvars.iv, -1
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%9 = icmp eq i64 %indvars.iv, 0
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br i1 %9, label %do.end, label %do.body3
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do.end: ; preds = %do.body3
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%dec24 = add nsw i32 %m.0, -1
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%tobool25 = icmp eq i32 %m.0, 0
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br i1 %tobool25, label %do.end26, label %do.body
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do.end26: ; preds = %do.end
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%arrayidx28 = getelementptr inbounds i32, i32* %localArg.sroa.0.0.copyload, i64 %0
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store i32 0, i32* %arrayidx28, align 4
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ret void
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; CHECK-LABEL: @big_loop_cold_innerloop
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; CHECK: mtctr
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; PWR: .p2align 5
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; CHECK-NOT: .p2align 5
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; CHECK: bdnz
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}
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