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[X86] Add the AVX storeu intrinsics to InstCombine and LoopStrengthReduce in the same places that the SSE/SSE2 storeu intrinsics appear.

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I don't really know how to test this. Just seemed like we should be consistent.

llvm-svn: 270819
This commit is contained in:
Craig Topper 2016-05-26 04:28:45 +00:00
parent 2baf0e57b1
commit b6c098560d
2 changed files with 19 additions and 0 deletions
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13
lib/Transforms/InstCombine/InstCombineCalls.cpp
View File

@ -1428,6 +1428,19 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
}
break;
case Intrinsic::x86_avx_storeu_ps_256:
case Intrinsic::x86_avx_storeu_pd_256:
case Intrinsic::x86_avx_storeu_dq_256:
// Turn X86 storeu -> store if the pointer is known aligned.
if (getOrEnforceKnownAlignment(II->getArgOperand(0), 32, DL, II, AC, DT) >=
32) {
Type *OpPtrTy =
PointerType::getUnqual(II->getArgOperand(1)->getType());
Value *Ptr = Builder->CreateBitCast(II->getArgOperand(0), OpPtrTy);
return new StoreInst(II->getArgOperand(1), Ptr);
}
break;
case Intrinsic::x86_vcvtph2ps_128:
case Intrinsic::x86_vcvtph2ps_256: {
auto Arg = II->getArgOperand(0);

6
lib/Transforms/Scalar/LoopStrengthReduce.cpp
View File

@ -687,6 +687,9 @@ static bool isAddressUse(Instruction *Inst, Value *OperandVal) {
case Intrinsic::x86_sse_storeu_ps:
case Intrinsic::x86_sse2_storeu_pd:
case Intrinsic::x86_sse2_storeu_dq:
case Intrinsic::x86_avx_storeu_ps_256:
case Intrinsic::x86_avx_storeu_pd_256:
case Intrinsic::x86_avx_storeu_dq_256:
if (II->getArgOperand(0) == OperandVal)
isAddress = true;
break;
@ -711,6 +714,9 @@ static MemAccessTy getAccessType(const Instruction *Inst) {
case Intrinsic::x86_sse_storeu_ps:
case Intrinsic::x86_sse2_storeu_pd:
case Intrinsic::x86_sse2_storeu_dq:
case Intrinsic::x86_avx_storeu_ps_256:
case Intrinsic::x86_avx_storeu_pd_256:
case Intrinsic::x86_avx_storeu_dq_256:
AccessTy.MemTy = II->getArgOperand(0)->getType();
break;
}