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[AArch64][GlobalISel] Use wzr/xzr for 16 and 32 bit stores of zero
We weren't performing this optimization on 16 and 32 bit stores. SDAG happily does this though. e.g. https://godbolt.org/z/cWocKr This saves about 0.2% in code size on CTMark at -O3. Differential Revision: https://reviews.llvm.org/D84568
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@ -2306,10 +2306,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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// If we're storing a 0, use WZR/XZR.
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if (auto CVal = getConstantVRegVal(ValReg, MRI)) {
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if (*CVal == 0 && Opcode == TargetOpcode::G_STORE) {
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if (I.getOpcode() == AArch64::STRWui)
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I.getOperand(0).setReg(AArch64::WZR);
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else if (I.getOpcode() == AArch64::STRXui)
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I.getOperand(0).setReg(AArch64::XZR);
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unsigned Opc = I.getOpcode();
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switch(Opc) {
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case AArch64::STRWui:
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case AArch64::STRHHui:
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case AArch64::STRBBui:
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I.getOperand(0).setReg(AArch64::WZR);
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break;
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case AArch64::STRXui:
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I.getOperand(0).setReg(AArch64::XZR);
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break;
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}
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}
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}
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@ -11,6 +11,8 @@
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define void @store_zero_s64_gpr(i64* %addr) { ret void }
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define void @store_zero_s32_gpr(i32* %addr) { ret void }
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define void @store_zero_s16(i32* %addr) { ret void }
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define void @store_zero_s8(i32* %addr) { ret void }
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define void @store_fi_s64_gpr() {
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%ptr0 = alloca i64
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@ -176,6 +178,37 @@ body: |
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...
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---
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name: store_zero_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: store_zero_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: STRHHui $wzr, [[COPY]], 0 :: (store 2)
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%0:gpr(p0) = COPY $x0
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%1:gpr(s16) = G_CONSTANT i16 0
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G_STORE %1(s16), %0(p0) :: (store 2)
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...
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---
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name: store_zero_s8
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: store_zero_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: STRBBui $wzr, [[COPY]], 0 :: (store 1)
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%0:gpr(p0) = COPY $x0
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%1:gpr(s8) = G_CONSTANT i8 0
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G_STORE %1(s8), %0(p0) :: (store 1)
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...
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---
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name: store_fi_s64_gpr
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legalized: true
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