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[Hexagon] Generate better splat code on v62+
This commit is contained in:
Krzysztof Parzyszek
parent
4f6d45dd89
commit
b743f9e32b
@ -199,32 +199,61 @@ let Predicates = [UseHVX] in {
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(V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
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}
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def Vsplatib: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatB $V)))>;
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def Vsplatih: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatH $V)))>;
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def Vsplatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
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// Splats for HvxV60
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def V60splatib: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatB $V)))>;
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def V60splatih: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 (SplatH $V)))>;
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def V60splatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
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def V60splatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
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def V60splatrh: OutPatFrag<(ops node:$Rs),
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(V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
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def V60splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
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def Vsplatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
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def Vsplatrh: OutPatFrag<(ops node:$Rs),
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(V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
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def Vsplatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
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// Splats for HvxV62+
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def V62splatib: OutPatFrag<(ops node:$V), (V6_lvsplatb (ToI32 $V))>;
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def V62splatih: OutPatFrag<(ops node:$V), (V6_lvsplath (ToI32 $V))>;
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def V62splatiw: OutPatFrag<(ops node:$V), (V6_lvsplatw (ToI32 $V))>;
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def V62splatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatb $Rs)>;
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def V62splatrh: OutPatFrag<(ops node:$Rs), (V6_lvsplath $Rs)>;
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def V62splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
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def Rep: OutPatFrag<(ops node:$N), (Combinev $N, $N)>;
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let Predicates = [UseHVX] in {
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let Predicates = [UseHVX,UseHVXV60] in {
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let AddedComplexity = 10 in {
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def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (Vsplatib $V)>;
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def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (Vsplatih $V)>;
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def: Pat<(VecI32 (splat_vector anyimm:$V)), (Vsplatiw $V)>;
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def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)), (Rep (Vsplatib $V))>;
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def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)), (Rep (Vsplatih $V))>;
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def: Pat<(VecPI32 (splat_vector anyimm:$V)), (Rep (Vsplatiw $V))>;
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def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (V60splatib $V)>;
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def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (V60splatih $V)>;
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def: Pat<(VecI32 (splat_vector anyimm:$V)), (V60splatiw $V)>;
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def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)), (Rep (V60splatib $V))>;
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def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)), (Rep (V60splatih $V))>;
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def: Pat<(VecPI32 (splat_vector anyimm:$V)), (Rep (V60splatiw $V))>;
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}
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def: Pat<(VecI8 (splat_vector I32:$Rs)), (V60splatrb $Rs)>;
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def: Pat<(VecI16 (splat_vector I32:$Rs)), (V60splatrh $Rs)>;
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def: Pat<(VecI32 (splat_vector I32:$Rs)), (V60splatrw $Rs)>;
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def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (V60splatrb $Rs))>;
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def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (V60splatrh $Rs))>;
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def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (V60splatrw $Rs))>;
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}
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let Predicates = [UseHVX,UseHVXV62] in {
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let AddedComplexity = 30 in {
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def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (V62splatib imm:$V)>;
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def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (V62splatih imm:$V)>;
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def: Pat<(VecI32 (splat_vector anyimm:$V)), (V62splatiw imm:$V)>;
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def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)),
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(Rep (V62splatib imm:$V))>;
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def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)),
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(Rep (V62splatih imm:$V))>;
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def: Pat<(VecPI32 (splat_vector anyimm:$V)),
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(Rep (V62splatiw imm:$V))>;
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}
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let AddedComplexity = 20 in {
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def: Pat<(VecI8 (splat_vector I32:$Rs)), (V62splatrb $Rs)>;
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def: Pat<(VecI16 (splat_vector I32:$Rs)), (V62splatrh $Rs)>;
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def: Pat<(VecI32 (splat_vector I32:$Rs)), (V62splatrw $Rs)>;
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def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (V62splatrb $Rs))>;
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def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (V62splatrh $Rs))>;
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def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (V62splatrw $Rs))>;
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}
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def: Pat<(VecI8 (splat_vector I32:$Rs)), (Vsplatrb $Rs)>;
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def: Pat<(VecI16 (splat_vector I32:$Rs)), (Vsplatrh $Rs)>;
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def: Pat<(VecI32 (splat_vector I32:$Rs)), (Vsplatrw $Rs)>;
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def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (Vsplatrb $Rs))>;
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def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (Vsplatrh $Rs))>;
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def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (Vsplatrw $Rs))>;
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}
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class Vneg1<ValueType VecTy>
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@ -425,10 +454,18 @@ let Predicates = [UseHVX] in {
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def: Pat<(VecPI32 (vunpacku HVI8:$Vs)), (VZxth (LoVec (VZxtb $Vs)))>;
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def: Pat<(VecPI32 (vunpacku HVI32:$Vs)), (VZxth $Vs)>;
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def: Pat<(VecI16 (bswap HVI16:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
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def: Pat<(VecI32 (bswap HVI32:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
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let Predicates = [UseHVX,UseHVXV60] in {
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def: Pat<(VecI16 (bswap HVI16:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V60splatib (i32 0x01)))>;
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def: Pat<(VecI32 (bswap HVI32:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V60splatib (i32 0x03)))>;
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}
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let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in {
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def: Pat<(VecI16 (bswap HVI16:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V62splatib (i32 0x01)))>;
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def: Pat<(VecI32 (bswap HVI32:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V62splatib (i32 0x03)))>;
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}
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def: Pat<(VecI8 (ctpop HVI8:$Vs)),
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(V6_vpackeb (V6_vpopcounth (HiVec (V6_vunpackub HvxVR:$Vs))),
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@ -438,10 +475,17 @@ let Predicates = [UseHVX] in {
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(V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))),
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(HiVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))))>;
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let Predicates = [UseHVX,UseHVXV60] in
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def: Pat<(VecI8 (ctlz HVI8:$Vs)),
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(V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
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(V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
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(V6_lvsplatw (A2_tfrsi 0x08080808)))>;
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(V60splatib (i32 0x08)))>;
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let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in
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def: Pat<(VecI8 (ctlz HVI8:$Vs)),
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(V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
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(V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
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(V62splatib (i32 0x08)))>;
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def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>;
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def: Pat<(VecI32 (ctlz HVI32:$Vs)), (V6_vcl0w HvxVR:$Vs)>;
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}
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401
test/CodeGen/Hexagon/autohvx/splat.ll
Normal file
401
test/CodeGen/Hexagon/autohvx/splat.ll
Normal file
@ -0,0 +1,401 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Splat immediate, 8-bit, v60
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define <128 x i8> @f0() #0 {
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; CHECK-LABEL: f0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = ##2139062143
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <128 x i8> undef, i8 127, i32 0
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%v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
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ret <128 x i8> %v1
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}
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; Splat immediate, 16 bit, v60
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define <64 x i16> @f1() #0 {
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; CHECK-LABEL: f1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = ##-1437226411
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <64 x i16> undef, i16 43605, i32 0
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%v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
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ret <64 x i16> %v1
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}
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; Splat immediate, 32 bit, v60
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define <32 x i32> @f2() #0 {
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; CHECK-LABEL: f2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = ##134744072
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <32 x i32> undef, i32 134744072, i32 0
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%v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
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ret <32 x i32> %v1
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}
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; Splat immediate, 8-bit, v62+
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define <128 x i8> @f3() #1 {
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; CHECK-LABEL: f3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = #127
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <128 x i8> undef, i8 127, i32 0
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%v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
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ret <128 x i8> %v1
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}
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; Splat immediate, 16 bit, v62+
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define <64 x i16> @f4() #1 {
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; CHECK-LABEL: f4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = #-21931
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <64 x i16> undef, i16 43605, i32 0
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%v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
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ret <64 x i16> %v1
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}
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; Splat immediate, 32 bit, v62+
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define <32 x i32> @f5() #1 {
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; CHECK-LABEL: f5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = ##134744072
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <32 x i32> undef, i32 134744072, i32 0
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%v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
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ret <32 x i32> %v1
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}
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; Splat register, 8-bit, v60
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define <128 x i8> @f6(i8 %a0) #0 {
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; CHECK-LABEL: f6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = vsplatb(r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <128 x i8> undef, i8 %a0, i32 0
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%v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
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ret <128 x i8> %v1
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}
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; Splat register, 16 bit, v60
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define <64 x i16> @f7(i16 %a0) #0 {
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; CHECK-LABEL: f7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = combine(r0.l,r0.l)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <64 x i16> undef, i16 %a0, i32 0
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%v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
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ret <64 x i16> %v1
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}
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; Splat register, 32 bit, v60
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define <32 x i32> @f8(i32 %a0) #0 {
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; CHECK-LABEL: f8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <32 x i32> undef, i32 %a0, i32 0
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%v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
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ret <32 x i32> %v1
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}
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; Splat register, 8-bit, v62+
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define <128 x i8> @f9(i8 %a0) #1 {
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; CHECK-LABEL: f9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <128 x i8> undef, i8 %a0, i32 0
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%v1 = shufflevector <128 x i8> %v0, <128 x i8> undef, <128 x i32> zeroinitializer
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ret <128 x i8> %v1
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}
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; Splat register, 16 bit, v62+
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define <64 x i16> @f10(i16 %a0) #1 {
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; CHECK-LABEL: f10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <64 x i16> undef, i16 %a0, i32 0
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%v1 = shufflevector <64 x i16> %v0, <64 x i16> undef, <64 x i32> zeroinitializer
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ret <64 x i16> %v1
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}
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; Splat register, 32 bit, v62+
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define <32 x i32> @f11(i32 %a0) #1 {
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; CHECK-LABEL: f11:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vsplat(r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <32 x i32> undef, i32 %a0, i32 0
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%v1 = shufflevector <32 x i32> %v0, <32 x i32> undef, <32 x i32> zeroinitializer
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ret <32 x i32> %v1
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}
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; Splat immediate, 8-bit, v60, pair
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define <256 x i8> @f12() #0 {
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; CHECK-LABEL: f12:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = ##2139062143
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1 = vsplat(r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = v1
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <256 x i8> undef, i8 127, i32 0
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%v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
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ret <256 x i8> %v1
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}
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; Splat immediate, 16 bit, v60, pair
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define <128 x i16> @f13() #0 {
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; CHECK-LABEL: f13:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = ##-1437226411
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <128 x i16> undef, i16 43605, i32 0
|
||||
%v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
|
||||
ret <128 x i16> %v1
|
||||
}
|
||||
|
||||
; Splat immediate, 32 bit, v60, pair
|
||||
define <64 x i32> @f14() #0 {
|
||||
; CHECK-LABEL: f14:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = ##134744072
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <64 x i32> undef, i32 134744072, i32 0
|
||||
%v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
|
||||
ret <64 x i32> %v1
|
||||
}
|
||||
|
||||
; Splat immediate, 8-bit, v62+, pair
|
||||
define <256 x i8> @f15() #1 {
|
||||
; CHECK-LABEL: f15:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = #127
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1.b = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <256 x i8> undef, i8 127, i32 0
|
||||
%v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
|
||||
ret <256 x i8> %v1
|
||||
}
|
||||
|
||||
; Splat immediate, 16 bit, v62+, pair
|
||||
define <128 x i16> @f16() #1 {
|
||||
; CHECK-LABEL: f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = #-21931
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1.h = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <128 x i16> undef, i16 43605, i32 0
|
||||
%v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
|
||||
ret <128 x i16> %v1
|
||||
}
|
||||
|
||||
; Splat immediate, 32 bit, v62+, pair
|
||||
define <64 x i32> @f17() #1 {
|
||||
; CHECK-LABEL: f17:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = ##134744072
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <64 x i32> undef, i32 134744072, i32 0
|
||||
%v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
|
||||
ret <64 x i32> %v1
|
||||
}
|
||||
|
||||
; Splat register, 8-bit, v60, pair
|
||||
define <256 x i8> @f18(i8 %a0) #0 {
|
||||
; CHECK-LABEL: f18:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = vsplatb(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <256 x i8> undef, i8 %a0, i32 0
|
||||
%v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
|
||||
ret <256 x i8> %v1
|
||||
}
|
||||
|
||||
; Splat register, 16 bit, v60, pair
|
||||
define <128 x i16> @f19(i16 %a0) #0 {
|
||||
; CHECK-LABEL: f19:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r0 = combine(r0.l,r0.l)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <128 x i16> undef, i16 %a0, i32 0
|
||||
%v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
|
||||
ret <128 x i16> %v1
|
||||
}
|
||||
|
||||
; Splat register, 32 bit, v60, pair
|
||||
define <64 x i32> @f20(i32 %a0) #0 {
|
||||
; CHECK-LABEL: f20:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <64 x i32> undef, i32 %a0, i32 0
|
||||
%v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
|
||||
ret <64 x i32> %v1
|
||||
}
|
||||
|
||||
; Splat register, 8-bit, v62+, pair
|
||||
define <256 x i8> @f21(i8 %a0) #1 {
|
||||
; CHECK-LABEL: f21:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1.b = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <256 x i8> undef, i8 %a0, i32 0
|
||||
%v1 = shufflevector <256 x i8> %v0, <256 x i8> undef, <256 x i32> zeroinitializer
|
||||
ret <256 x i8> %v1
|
||||
}
|
||||
|
||||
; Splat register, 16 bit, v62+, pair
|
||||
define <128 x i16> @f22(i16 %a0) #1 {
|
||||
; CHECK-LABEL: f22:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1.h = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <128 x i16> undef, i16 %a0, i32 0
|
||||
%v1 = shufflevector <128 x i16> %v0, <128 x i16> undef, <128 x i32> zeroinitializer
|
||||
ret <128 x i16> %v1
|
||||
}
|
||||
|
||||
; Splat register, 32 bit, v62+, pair
|
||||
define <64 x i32> @f23(i32 %a0) #1 {
|
||||
; CHECK-LABEL: f23:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v1 = vsplat(r0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = v1
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <64 x i32> undef, i32 %a0, i32 0
|
||||
%v1 = shufflevector <64 x i32> %v0, <64 x i32> undef, <64 x i32> zeroinitializer
|
||||
ret <64 x i32> %v1
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
|
||||
attributes #1 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length128b" }
|
||||
Loading…
Reference in New Issue
Block a user