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[AArch64] Preserve register flags when promoting a load from store.

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Summary:
This patch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved. 

This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468). 


Reviewers: MatzeB, t.p.northover, junbuml

Reviewed By: MatzeB

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34402

llvm-svn: 305885
This commit is contained in:
Florian Hahn 2017-06-21 08:47:23 +00:00
parent c35ff985b1
commit b76b00f3a8
2 changed files with 23 additions and 4 deletions
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7
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
View File

@ -795,6 +795,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
int LoadSize = getMemScale(*LoadI);
int StoreSize = getMemScale(*StoreI);
unsigned LdRt = getLdStRegOp(*LoadI).getReg();
const MachineOperand &StMO = getLdStRegOp(*StoreI);
unsigned StRt = getLdStRegOp(*StoreI).getReg();
bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
@ -819,7 +820,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
.addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
.addReg(StRt)
.add(StMO)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
} else {
// FIXME: Currently we disable this transformation in big-endian targets as
@ -860,14 +861,14 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
DestReg)
.addReg(StRt)
.add(StMO)
.addImm(AndMaskEncoded);
} else {
BitExtMI =
BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
DestReg)
.addReg(StRt)
.add(StMO)
.addImm(Immr)
.addImm(Imms);
}

20
test/CodeGen/AArch64/ldst-opt.mir
View File

@ -34,7 +34,7 @@ body: |
# Don't count transient instructions towards search limits.
# CHECK-LABEL: name: promote-load-from-store
# CHECK: STRWui %w1
# CHECK: UBFMWri %w1
# CHECK: UBFMWri killed %w1
---
name: store-pair
tracksRegLiveness: true
@ -144,3 +144,21 @@ body: |
# CHECK: %wzr = COPY %w1
# CHECK: %w11 = ORRWrs %wzr, %w1, 0
# CHECK: HINT 0, implicit %w11
---
name: promote-load-from-store-undef
tracksRegLiveness: true
body: |
bb.0:
liveins: %x0, %x2, %lr
STRWui undef %w1, %x0, 0 :: (store 4)
%w0 = LDRBBui %x0, 1 :: (load 2)
STRHHui undef %w3, %x2, 0 :: (store 4)
%w1 = LDRBBui %x2, 0 :: (load 4)
RET %lr, implicit %w0
...
# CHECK-LABEL: name: promote-load-from-store-undef
# CHECK: STRWui undef %w1
# CHECK: UBFMWri undef %w1
# CHECK: STRHHui undef %w3
# CHECK: ANDWri undef %w3