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[Codegen] Revert rL354676/rL354677 and followups - introduced PR43446 miscompile

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This reverts https://reviews.llvm.org/D58468
(rL354676, 44037d7a6377ec8e5542cced73583283334b516b),
and all and any follow-ups to that code block.

https://bugs.llvm.org/show_bug.cgi?id=43446
This commit is contained in:
Roman Lebedev 2020-02-25 20:08:58 +03:00
parent c7f8ce0cc2
commit b7853e852c
7 changed files with 47 additions and 43 deletions
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27
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -16623,33 +16623,6 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
CombineTo(ST1, ST1->getChain());
return SDValue();
}
// If ST stores to a subset of preceding store's write set, we may be
// able to fold ST's value into the preceding stored value. As we know
// the other uses of ST1's chain are unconcerned with ST, this folding
// will not affect those nodes.
int64_t BitOffset;
if (ChainBase.contains(DAG, ChainBitSize, STBase, STBitSize,
BitOffset)) {
SDValue ChainValue = ST1->getValue();
if (auto *C1 = dyn_cast<ConstantSDNode>(ChainValue)) {
if (auto *C = dyn_cast<ConstantSDNode>(Value)) {
APInt Val = C1->getAPIntValue();
APInt InsertVal = C->getAPIntValue().zextOrTrunc(STBitSize);
// FIXME: Handle Big-endian mode.
if (!DAG.getDataLayout().isBigEndian()) {
Val.insertBits(InsertVal, BitOffset);
SDValue NewSDVal =
DAG.getConstant(Val, SDLoc(C), ChainValue.getValueType(),
C1->isTargetOpcode(), C1->isOpaque());
SDNode *NewST1 = DAG.UpdateNodeOperands(
ST1, ST1->getChain(), NewSDVal, ST1->getOperand(2),
ST1->getOperand(3));
return CombineTo(ST, SDValue(NewST1, 0));
}
}
}
} // End ST subset of ST1 case.
}
}
}

31
test/CodeGen/AArch64/ldst-paired-aliasing.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
target triple = "aarch64--linux-gnu"
@ -10,11 +11,33 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3
define i32 @main() local_unnamed_addr #1 {
; Make sure the stores happen in the correct order (the exact instructions could change).
; CHECK-LABEL: main:
; CHECK: // %bb.0: // %for.body.lr.ph.i.i.i.i.i.i63
; CHECK-NEXT: sub sp, sp, #112 // =112
; CHECK-NEXT: str x30, [sp, #96] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl _Z5setupv
; CHECK-NEXT: movi v0.4s, #1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: add x0, sp, #48 // =48
; CHECK-NEXT: mov x1, sp
; CHECK-NEXT: str xzr, [sp, #80]
; CHECK-NEXT: str w9, [sp, #80]
; CHECK-NEXT: stp q0, q0, [sp, #48]
; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: cmp w8, #1 // =1
; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: // %bb.1: // %for.inc
; CHECK-NEXT: bl f
; CHECK-NEXT: b .LBB0_3
; CHECK-NEXT: .LBB0_2: // %if.then
; CHECK-NEXT: bl f2
; CHECK-NEXT: .LBB0_3: // %for.inc
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: add sp, sp, #112 // =112
; CHECK-NEXT: ret
; CHECK: mov w9, #1
; CHECK: str x9, [sp, #80]
; CHECK: stp q0, q0, [sp, #48]
; CHECK: ldr w8, [sp, #48]
for.body.lr.ph.i.i.i.i.i.i63:
%b1 = alloca [10 x i32], align 16

8
test/CodeGen/PowerPC/constant-combines.ll
View File

@ -13,8 +13,10 @@ define void @fold_constant_stores_loaddr(i8* %i8_ptr) {
;
; LE-LABEL: fold_constant_stores_loaddr:
; LE: # %bb.0: # %entry
; LE-NEXT: li 4, 170
; LE-NEXT: li 4, 0
; LE-NEXT: li 5, -86
; LE-NEXT: std 4, 0(3)
; LE-NEXT: stb 5, 0(3)
; LE-NEXT: blr
entry:
%i64_ptr = bitcast i8* %i8_ptr to i64*
@ -35,8 +37,10 @@ define void @fold_constant_stores_hiaddr(i8* %i8_ptr) {
;
; LE-LABEL: fold_constant_stores_hiaddr:
; LE: # %bb.0: # %entry
; LE-NEXT: li 4, 170
; LE-NEXT: li 4, 0
; LE-NEXT: li 5, -86
; LE-NEXT: std 4, 0(3)
; LE-NEXT: stb 5, 0(3)
; LE-NEXT: blr
entry:
%i64_ptr = bitcast i8* %i8_ptr to i64*

3
test/CodeGen/X86/constant-combines.ll
View File

@ -7,7 +7,8 @@ target triple = "x86_64-unknown-unknown"
define void @bitstore_fold() {
; CHECK-LABEL: bitstore_fold:
; CHECK: # %bb.0: # %BB
; CHECK-NEXT: movl $-2, 0
; CHECK-NEXT: movl $-1, 0
; CHECK-NEXT: movb $0, 0
; CHECK-NEXT: retq
BB:
store i32 -1, i32* null

10
test/CodeGen/X86/lifetime-alias.ll
View File

@ -23,7 +23,7 @@ target triple = "x86_64-unknown-linux-gnu"
@__PRETTY_FUNCTION__.main = private unnamed_addr constant [11 x i8] c"int main()\00", align 1
; Function Attrs: norecurse uwtable
define dso_local i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50
; CHECK-NEXT: pushq %rax
@ -35,6 +35,8 @@ define dso_local i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (
; CHECK-NEXT: movw $5632, {{[0-9]+}}(%rsp) # imm = 0x1600
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $11, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $8389209137051166804, %rax # imm = 0x746C754320656854
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl $1701999988, -{{[0-9]+}}(%rsp) # imm = 0x65727574
@ -47,7 +49,7 @@ define dso_local i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (
; CHECK-NEXT: movups {{.*}}(%rip), %xmm1
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $792633534417207296, %rax # imm = 0xB00000000000000
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
@ -68,9 +70,9 @@ define dso_local i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rax, .Ldo_not_optimize${{.*}}(%rip)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rax, .Ldo_not_optimize${{.*}}(%rip)
; CHECK-NEXT: cmpb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: jns .LBB0_1
; CHECK-NEXT: # %bb.2: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50

3
test/CodeGen/X86/pr40631_deadstore_elision.ll
View File

@ -12,12 +12,13 @@ define i32 @ipt_do_table(%struct.sk_buff* noalias nocapture readonly) {
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $170, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [12297829382473034410,12297829382473034410]
; CHECK-NEXT: movaps %xmm0, (%rsp)
; CHECK-NEXT: movabsq $-6148914691236517206, %rcx # imm = 0xAAAAAAAAAAAAAAAA
; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $-86, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movzwl 2(%rax), %ecx
; CHECK-NEXT: andl $8191, %ecx # imm = 0x1FFF
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%rsp)

8
test/CodeGen/X86/stores-merging.ll
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@ -26,8 +26,9 @@ define void @redundant_stores_merging() {
define void @redundant_stores_merging_reverse() {
; CHECK-LABEL: redundant_stores_merging_reverse:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $1958505086977, %rax # imm = 0x1C800000001
; CHECK-NEXT: movabsq $528280977409, %rax # imm = 0x7B00000001
; CHECK-NEXT: movq %rax, e+{{.*}}(%rip)
; CHECK-NEXT: movl $456, e+{{.*}}(%rip) # imm = 0x1C8
; CHECK-NEXT: retq
store i32 123, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 2), align 4
store i32 456, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 2), align 4
@ -219,12 +220,11 @@ define void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #
ret void
}
; These are miscompiles - we should store '1', not '-1'.
; https://bugs.llvm.org/show_bug.cgi?id=43446
define void @pr43446_0(i64 %x) {
; CHECK-LABEL: pr43446_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movb $-1, (%rdi)
; CHECK-NEXT: movb $1, (%rdi)
; CHECK-NEXT: retq
%a = inttoptr i64 %x to i8*
store i8 -2, i8* %a, align 1
@ -235,7 +235,7 @@ define void @pr43446_0(i64 %x) {
define void @pr43446_1(i8* %a) {
; CHECK-LABEL: pr43446_1:
; CHECK: # %bb.0:
; CHECK-NEXT: movb $-1, (%rdi)
; CHECK-NEXT: movb $1, (%rdi)
; CHECK-NEXT: retq
store i8 -2, i8* %a, align 1
%b = bitcast i8* %a to i1*