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[PowerPC] Reduce symmetrical swaps for lane-insensitive vector ops
This patch simplifies pattern (xxswap (vec-op (xxswap a) (xxswap b))) into (vec-op a b) if vec-op is lane-insensitive. The motivating case is ScalarToVector-VecOp-ExtractElement sequence on LE, but the peephole itself is not related to endianness, so BE may also benefit from this. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D97658
This commit is contained in:
Qiu Chaofan
parent
f70507366d
commit
b78bd4345c
@ -6717,6 +6717,102 @@ void PPCDAGToDAGISel::PeepholePPC64ZExt() {
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CurDAG->RemoveDeadNodes();
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}
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static bool isVSXSwap(SDValue N) {
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if (!N->isMachineOpcode())
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return false;
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unsigned Opc = N->getMachineOpcode();
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// Single-operand XXPERMDI or the regular XXPERMDI/XXSLDWI where the immediate
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// operand is 2.
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if (Opc == PPC::XXPERMDIs) {
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return isa<ConstantSDNode>(N->getOperand(1)) &&
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N->getConstantOperandVal(1) == 2;
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} else if (Opc == PPC::XXPERMDI || Opc == PPC::XXSLDWI) {
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return N->getOperand(0) == N->getOperand(1) &&
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isa<ConstantSDNode>(N->getOperand(2)) &&
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N->getConstantOperandVal(2) == 2;
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}
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return false;
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}
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// TODO: Make this complete and replace with a table-gen bit.
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static bool isLaneInsensitive(SDValue N) {
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if (!N->isMachineOpcode())
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return false;
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unsigned Opc = N->getMachineOpcode();
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switch (Opc) {
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default:
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return false;
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case PPC::VAVGSB:
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case PPC::VAVGUB:
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case PPC::VAVGSH:
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case PPC::VAVGUH:
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case PPC::VAVGSW:
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case PPC::VAVGUW:
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case PPC::VMAXFP:
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case PPC::VMAXSB:
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case PPC::VMAXUB:
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case PPC::VMAXSH:
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case PPC::VMAXUH:
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case PPC::VMAXSW:
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case PPC::VMAXUW:
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case PPC::VMINFP:
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case PPC::VMINSB:
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case PPC::VMINUB:
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case PPC::VMINSH:
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case PPC::VMINUH:
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case PPC::VMINSW:
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case PPC::VMINUW:
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case PPC::VADDFP:
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case PPC::VADDUBM:
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case PPC::VADDUHM:
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case PPC::VADDUWM:
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case PPC::VSUBFP:
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case PPC::VSUBUBM:
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case PPC::VSUBUHM:
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case PPC::VSUBUWM:
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case PPC::VAND:
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case PPC::VANDC:
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case PPC::VOR:
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case PPC::VORC:
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case PPC::VXOR:
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case PPC::VNOR:
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case PPC::VMULUWM:
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return true;
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}
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}
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// Try to simplify (xxswap (vec-op (xxswap) (xxswap))) where vec-op is
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// lane-insensitive.
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static void reduceVSXSwap(SDNode *N, SelectionDAG *DAG) {
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// Our desired xxswap might be source of COPY_TO_REGCLASS.
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// TODO: Can we put this a common method for DAG?
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auto SkipRCCopy = [](SDValue V) {
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while (V->isMachineOpcode() &&
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V->getMachineOpcode() == TargetOpcode::COPY_TO_REGCLASS)
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V = V->getOperand(0);
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return V;
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};
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SDValue VecOp = SkipRCCopy(N->getOperand(0));
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if (!isLaneInsensitive(VecOp))
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return;
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SDValue LHS = SkipRCCopy(VecOp.getOperand(0)),
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RHS = SkipRCCopy(VecOp.getOperand(1));
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if (!LHS.hasOneUse() || !RHS.hasOneUse() || !isVSXSwap(LHS) ||
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!isVSXSwap(RHS))
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return;
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// These swaps may still have chain-uses here, count on dead code elimination
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// in following passes to remove them.
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DAG->ReplaceAllUsesOfValueWith(LHS, LHS.getOperand(0));
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DAG->ReplaceAllUsesOfValueWith(RHS, RHS.getOperand(0));
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DAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), N->getOperand(0));
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}
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void PPCDAGToDAGISel::PeepholePPC64() {
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SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
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@ -6726,6 +6822,9 @@ void PPCDAGToDAGISel::PeepholePPC64() {
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if (N->use_empty() || !N->isMachineOpcode())
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continue;
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if (isVSXSwap(SDValue(N, 0)))
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reduceVSXSwap(N, CurDAG);
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unsigned FirstOp;
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unsigned StorageOpcode = N->getMachineOpcode();
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bool RequiresMod4Offset = false;
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58
test/CodeGen/PowerPC/swap-reduction.ll
Normal file
58
test/CodeGen/PowerPC/swap-reduction.ll
Normal file
@ -0,0 +1,58 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le < %s | FileCheck %s
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define i64 @test1(i64* %a, i64* %b) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 5, 3
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: ld 4, 0(4)
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; CHECK-NEXT: mtvsrd 34, 3
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; CHECK-NEXT: add 3, 3, 4
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; CHECK-NEXT: mtvsrd 35, 4
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; CHECK-NEXT: vavgsb 2, 2, 3
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; CHECK-NEXT: stxsdx 34, 0, 5
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; CHECK-NEXT: blr
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entry:
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%lhs = load i64, i64* %a, align 8
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%rhs = load i64, i64* %b, align 8
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%sum = add i64 %lhs, %rhs
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%lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
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%rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
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%lhc = bitcast <2 x i64> %lv to <16 x i8>
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%rhc = bitcast <2 x i64> %rv to <16 x i8>
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%add = call <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8> %lhc, <16 x i8> %rhc)
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%cb = bitcast <16 x i8> %add to <2 x i64>
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%fv = extractelement <2 x i64> %cb, i32 0
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store i64 %fv, i64* %a, align 8
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ret i64 %sum
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}
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define i64 @test2(i64* %a, i64* %b) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 5, 3
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: ld 4, 0(4)
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; CHECK-NEXT: mtvsrd 34, 3
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; CHECK-NEXT: add 3, 3, 4
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; CHECK-NEXT: mtvsrd 35, 4
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; CHECK-NEXT: vadduhm 2, 2, 3
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; CHECK-NEXT: stxsdx 34, 0, 5
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; CHECK-NEXT: blr
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entry:
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%lhs = load i64, i64* %a, align 8
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%rhs = load i64, i64* %b, align 8
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%sum = add i64 %lhs, %rhs
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%lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
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%rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
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%lhc = bitcast <2 x i64> %lv to <8 x i16>
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%rhc = bitcast <2 x i64> %rv to <8 x i16>
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%add = add <8 x i16> %lhc, %rhc
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%cb = bitcast <8 x i16> %add to <2 x i64>
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%fv = extractelement <2 x i64> %cb, i32 0
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store i64 %fv, i64* %a, align 8
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ret i64 %sum
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}
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declare <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8>, <16 x i8>)
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